Arria® V Device Datasheet

ID 683022
Date 5/23/2023
Document Table of Contents

1.3.4. Active Serial (AS) Configuration Timing

Table 68.  AS Timing Parameters for AS ×1 and ×4 Configurations in Arria® V Devices

The minimum and maximum numbers apply to both the internal oscillator and CLKUSR when either one is used as the clock source for device configuration.

The tCF2CD, tCF2ST0, tCFG, tSTATUS, and tCF2ST1 timing parameters are identical to the timing parameters for passive serial (PS) mode listed in PS Timing Parameters for Arria® V Devices table. You can obtain the tCF2ST1 value if you do not delay configuration by externally holding nSTATUS low.

Symbol Parameter Condition Minimum Maximum Unit
tCO 104 DCLK falling edge to the AS_DATA0/ASDO output 2 ns
tSU 105 Data setup time before the falling edge on DCLK 1.5 ns
tDH 105 Data hold time after the falling edge on DCLK –3 speed grade 1.7 ns
–4 speed grade 2.0 ns
–5 speed grade 2.3 ns
–6 speed grade 2.6 ns
tCD2UM CONF_DONE high to user mode 175 437 µs
tCD2CU CONF_DONE high to CLKUSR enabled 4 × maximum DCLK period
tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (Tinit × CLKUSR period)
Tinit Number of clock cycles required for device initialization 8,576 Cycles
104 Load capacitance for DCLK = 6 pF and AS_DATA/ASDO = 8 pF. Intel recommends obtaining the tCO for a given link (including receiver, transmission lines, connectors, termination resistors, and other components) through IBIS or HSPICE simulation.
105 To evaluate the data setup (tSU) and data hold time (tDH) slack on your board in order to ensure you are meeting the tSU and tDH requirement, Intel recommends following the guideline in the "Evaluating Data Setup and Hold Timing Slack" chapter in AN822: Intel FPGA Configuration Device Migration Guideline.

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