Arria® V Device Datasheet

ID 683022
Date 5/23/2023
Document Table of Contents FPP Configuration Timing when DCLK to DATA[] > 1

Figure 30. FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is >1 , Timing when using a MAX® II device, MAX® V device, or microprocessor as an external host.
Table 135.  FPP Timing Parameters for Arria V GZ Devices When the DCLK-to-DATA[] Ratio is >1Use these timing parameters when you use the decompression and design security features.
Symbol Parameter Minimum Maximum Unit
tCF2CD nCONFIG low to CONF_DONE low 600 ns
tCF2ST0 nCONFIG low to nSTATUS low 600 ns
tCFG nCONFIG low pulse width 2 μs
tSTATUS nSTATUS low pulse width 268 1,506 214 μs
tCF2ST1 nCONFIG high to nSTATUS high 1,506 215 μs
tCF2CK 216 nCONFIG high to first rising edge on DCLK 1,506 μs
tST2CK 216 nSTATUS high to first rising edge of DCLK 2 μs
tDSU DATA[] setup time before rising edge on DCLK 5.5 ns
tDH DATA[] hold time after rising edge on DCLK N–1/fDCLK 217 s
tCH DCLK high time 0.45 × 1/fMAX s
tCL DCLK low time 0.45 × 1/fMAX s
tCLK DCLK period 1/fMAX s
fMAX DCLK frequency (FPP  ×8/×16) 125 MHz
DCLK frequency (FPP  ×32) 100 MHz
tR Input rise time 40 ns
tF Input fall time 40 ns
tCD2UM CONF_DONE high to user mode 218 175 437 μs
tCD2CU CONF_DONE high to CLKUSR enabled 4 × maximum DCLK period
tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU +
(8576 × CLKUSR period) 219
214 You can obtain this value if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
215 You can obtain this value if you do not delay configuration by externally holding the nSTATUS low.
216 If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification.
217 N is the DCLK-to-DATA ratio and fDCLK is the DCLK frequency the system is operating.
218 The minimum and maximum numbers apply only if you use the internal oscillator as the clock source for initializing the device.
219 To enable the CLKUSR pin as the initialization clock source and to obtain the maximum frequency specification on these pins, refer to the Initialization section of the Configuration, Design Security, and Remote System Upgrades in Arria V Devices chapter.