Arria® V Device Datasheet

ID 683022
Date 5/23/2023
Document Table of Contents FPP Configuration Timing when DCLK to DATA[] = 1

Figure 29. FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is 1Timing waveform for FPP configuration when using a MAX® II or MAX® V device as an external host.
Note: When you enable the decompression or design security feature, the DCLK-to-DATA[] ratio varies for FPP ×8, FPP ×16, and FPP ×32. For the respective DCLK-to-DATA[] ratio, refer to the DCLK-to-DATA[] Ratio for Arria V GZ Devices table.
Table 134.  FPP Timing Parameters for Arria V GZ Devices When the DCLK-to-DATA[] Ratio is 1Use these timing parameters when the decompression and design security features are disabled.
Symbol Parameter Minimum Maximum Unit
tCF2CD nCONFIG low to CONF_DONE low 600 ns
tCF2ST0 nCONFIG low to nSTATUS low 600 ns
tCFG nCONFIG low pulse width 2 μs
tSTATUS nSTATUS low pulse width 268 1,506 209 μs
tCF2ST1 nCONFIG high to nSTATUS high 1,506 210 μs
tCF2CK 211 nCONFIG high to first rising edge on DCLK 1,506 μs
tST2CK 211 nSTATUS high to first rising edge of DCLK 2 μs
tDSU DATA[] setup time before rising edge on DCLK 5.5 ns
tDH DATA[] hold time after rising edge on DCLK 0 ns
tCH DCLK high time 0.45 × 1/fMAX s
tCL DCLK low time 0.45 × 1/fMAX s
tCLK DCLK period 1/fMAX s
fMAX DCLK frequency (FPP  ×8/×16) 125 MHz
DCLK frequency (FPP  ×32) 100 MHz
tCD2UM CONF_DONE high to user mode 212 175 437 μs
tCD2CU CONF_DONE high to CLKUSR enabled 4 × maximum

DCLK period

tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU +
(8576 × CLKUSR period) 213
209 This value is applicable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
210 This value is applicable if you do not delay configuration by externally holding the nSTATUS low.
211 If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification.
212 The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
213 To enable the CLKUSR pin as the initialization clock source and to obtain the maximum frequency specification on these pins, refer to the Initialization section of the Configuration, Design Security, and Remote System Upgrades in Arria V Devices chapter.