Arria® V Device Datasheet

ID 683022
Date 5/23/2023
Document Table of Contents FPP Configuration Timing when DCLK-to-DATA[] >1

Table 67.  FPP Timing Parameters When DCLK-to-DATA[] Ratio is >1 for Arria® V Devices

The specifications in this table are not applicable to Arria® V QS package.

Use these timing parameters when you use the decompression and design security features.

Symbol Parameter Minimum Maximum Unit
tCF2CD nCONFIG low to CONF_DONE low 600 ns
tCF2ST0 nCONFIG low to nSTATUS low 600 ns
tCFG nCONFIG low pulse width 2 µs
tSTATUS nSTATUS low pulse width 268 150699 µs
tCF2ST1 nCONFIG high to nSTATUS high 1506100 µs
tCF2CK 101 nCONFIG high to first rising edge on DCLK 1506 µs
tST2CK 101 nSTATUS high to first rising edge of DCLK 2 µs
tDSU DATA[] setup time before rising edge on DCLK 5.5 ns
tDH DATA[] hold time after rising edge on DCLK N – 1/fDCLK 102 s
tCH DCLK high time 0.45 × 1/fMAX s
tCL DCLK low time 0.45 × 1/fMAX s
tCLK DCLK period 1/fMAX s
fMAX DCLK frequency (FPP ×8/ ×16) 125 MHz
tR Input rise time 40 ns
tF Input fall time 40 ns
tCD2UM CONF_DONE high to user mode103 175 437 µs
tCD2CU CONF_DONE high to CLKUSR enabled 4 × maximum DCLK period
tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (Tinit × CLKUSR period)
Tinit Number of clock cycles required for device initialization 8,576 Cycles
99 This value can be obtained if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
100 This value can be obtained if you do not delay configuration by externally holding nSTATUS low.
101 If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification.
102 N is the DCLK-to-DATA[] ratio and fDCLK is the DCLK frequency of the system.
103 The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.