Arria® V Device Datasheet

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ID 683022
Date 5/23/2023
Public
Document Table of Contents
Document Table of Contents x
1. Arria® V GX, GT, SX, and ST Device Datasheet 2. Arria V GZ Device Datasheet
1. Arria® V GX, GT, SX, and ST Device Datasheet x
1.1. Electrical Characteristics 1.2. Switching Characteristics 1.3. Configuration Specifications 1.4. I/O Timing 1.5. Glossary 1.6. Arria® V GX, GT, SX, and ST Device Datasheet Revision History
1.1. Electrical Characteristics x
1.1.1. Operating Conditions
1.1.1. Operating Conditions x
1.1.1.1. Absolute Maximum Ratings 1.1.1.2. Maximum Allowed Overshoot and Undershoot Voltage 1.1.1.3. Recommended Operating Conditions 1.1.1.4. DC Characteristics 1.1.1.5. I/O Standard Specifications
1.1.1.3. Recommended Operating Conditions x
1.1.1.3.1. Recommended Operating Conditions 1.1.1.3.2. Transceiver Power Supply Operating Conditions 1.1.1.3.3. HPS Power Supply Operating Conditions
1.1.1.4. DC Characteristics x
1.1.1.4.1. Supply Current and Power Consumption 1.1.1.4.2. I/O Pin Leakage Current 1.1.1.4.3. Bus Hold Specifications 1.1.1.4.4. OCT Calibration Accuracy Specifications 1.1.1.4.5. OCT Without Calibration Resistance Tolerance Specifications 1.1.1.4.6. OCT Variation after Power-Up Calibration 1.1.1.4.7. Pin Capacitance 1.1.1.4.8. Hot Socketing 1.1.1.4.9. Internal Weak Pull-Up Resistor
1.1.1.5. I/O Standard Specifications x
1.1.1.5.1. Single-Ended I/O Standards 1.1.1.5.2. Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications 1.1.1.5.3. Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications 1.1.1.5.4. Differential SSTL I/O Standards 1.1.1.5.5. Differential HSTL and HSUL I/O Standards 1.1.1.5.6. Differential I/O Standard Specifications
1.2. Switching Characteristics x
1.2.1. Transceiver Performance Specifications 1.2.2. Core Performance Specifications 1.2.3. Periphery Performance 1.2.4. HPS Specifications
1.2.1. Transceiver Performance Specifications x
1.2.1.1. Transceiver Specifications for Arria V GX and SX Devices 1.2.1.2. Transceiver Specifications for Arria V GT and ST Devices 1.2.1.3. CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain 1.2.1.4. CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain 1.2.1.5. Typical TX VOD Setting for Arria® V Transceiver Channels with termination of 100 Ω 1.2.1.6. Transmitter Pre-Emphasis Levels 1.2.1.7. Transceiver Compliance Specification
1.2.2. Core Performance Specifications x
1.2.2.1. Clock Tree Specifications 1.2.2.2. PLL Specifications 1.2.2.3. DSP Block Performance Specifications 1.2.2.4. Memory Block Performance Specifications 1.2.2.5. Internal Temperature Sensing Diode Specifications
1.2.3. Periphery Performance x
1.2.3.1. High-Speed I/O Specifications 1.2.3.2. DPA Lock Time Specifications 1.2.3.3. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications 1.2.3.4. DLL Frequency Range Specifications 1.2.3.5. DQS Logic Block Specifications 1.2.3.6. Memory Output Clock Jitter Specifications 1.2.3.7. OCT Calibration Block Specifications 1.2.3.8. Duty Cycle Distortion (DCD) Specifications
1.2.4. HPS Specifications x
1.2.4.1. HPS Clock Performance 1.2.4.2. HPS PLL Specifications 1.2.4.3. Quad SPI Flash Timing Characteristics 1.2.4.4. SPI Timing Characteristics 1.2.4.5. SD/MMC Timing Characteristics 1.2.4.6. USB Timing Characteristics 1.2.4.7. Ethernet Media Access Controller (EMAC) Timing Characteristics 1.2.4.8. I2C Timing Characteristics 1.2.4.9. NAND Timing Characteristics 1.2.4.10. Arm* Trace Timing Characteristics 1.2.4.11. UART Interface 1.2.4.12. GPIO Interface 1.2.4.13. HPS JTAG Timing Specifications
1.2.4.2. HPS PLL Specifications x
1.2.4.2.1. HPS PLL VCO Frequency Range 1.2.4.2.2. HPS PLL Input Clock Range 1.2.4.2.3. HPS PLL Input Jitter
1.3. Configuration Specifications x
1.3.1. POR Specifications 1.3.2. FPGA JTAG Configuration Timing 1.3.3. FPP Configuration Timing 1.3.4. Active Serial (AS) Configuration Timing 1.3.5. DCLK Frequency Specification in the AS Configuration Scheme 1.3.6. Passive Serial (PS) Configuration Timing 1.3.7. Initialization 1.3.8. Configuration Files 1.3.9. Minimum Configuration Time Estimation 1.3.10. Remote System Upgrades 1.3.11. User Watchdog Internal Oscillator Frequency Specifications
1.3.3. FPP Configuration Timing x
1.3.3.1. DCLK-to-DATA[] Ratio (r) for FPP Configuration 1.3.3.2. FPP Configuration Timing when DCLK-to-DATA[] = 1 1.3.3.3. FPP Configuration Timing when DCLK-to-DATA[] >1
1.4. I/O Timing x
1.4.1. Programmable IOE Delay 1.4.2. Programmable Output Buffer Delay
2. Arria V GZ Device Datasheet x
2.1. Electrical Characteristics 2.2. Switching Characteristics 2.3. Configuration Specification 2.4. I/O Timing 2.5. Glossary 2.6. Arria® V GZ Device Datasheet Revision History
2.1. Electrical Characteristics x
2.1.1. Operating Conditions
2.1.1. Operating Conditions x
2.1.1.1. Absolute Maximum Ratings 2.1.1.2. Maximum Allowed Overshoot and Undershoot Voltage 2.1.1.3. Recommended Operating Conditions 2.1.1.4. DC Characteristics 2.1.1.5. I/O Standard Specifications
2.1.1.3. Recommended Operating Conditions x
2.1.1.3.1. Recommended Transceiver Power Supply Operating Conditions 2.1.1.3.2. Transceiver Power Supply Requirements
2.1.1.4. DC Characteristics x
2.1.1.4.1. Supply Current 2.1.1.4.2. Power Consumption 2.1.1.4.3. I/O Pin Leakage Current 2.1.1.4.4. Bus Hold Specifications 2.1.1.4.5. On-Chip Termination (OCT) Specifications 2.1.1.4.6. Pin Capacitance 2.1.1.4.7. Hot Socketing 2.1.1.4.8. Internal Weak Pull-Up Resistor
2.2. Switching Characteristics x
2.2.1. Transceiver Performance Specifications 2.2.2. Core Performance Specifications 2.2.3. Periphery Performance
2.2.1. Transceiver Performance Specifications x
2.2.1.1. Reference Clock 2.2.1.2. Transceiver Clocks 2.2.1.3. Receiver 2.2.1.4. Transmitter 2.2.1.5. CMU PLL 2.2.1.6. ATX PLL 2.2.1.7. Fractional PLL 2.2.1.8. Clock Network Data Rate 2.2.1.9. Standard PCS Data Rate 2.2.1.10. 10G PCS Data Rate 2.2.1.11. Typical VOD Settings
2.2.2. Core Performance Specifications x
2.2.2.1. Clock Tree Specifications 2.2.2.2. PLL Specifications 2.2.2.3. DSP Block Specifications 2.2.2.4. Memory Block Specifications 2.2.2.5. Temperature Sensing Diode Specifications
2.2.3. Periphery Performance x
2.2.3.1. High-Speed I/O Specification 2.2.3.2. DLL Range Specifications 2.2.3.3. DQS Logic Block Specifications 2.2.3.4. Memory Output Clock Jitter Specifications 2.2.3.5. OCT Calibration Block Specifications 2.2.3.6. Duty Cycle Distortion (DCD) Specifications
2.2.3.1. High-Speed I/O Specification x
2.2.3.1.1. High-Speed Clock Specifications 2.2.3.1.2. Transmitter High-Speed I/O Specifications 2.2.3.1.3. Receiver High-Speed I/O Specifications 2.2.3.1.4. DPA Mode High-Speed I/O Specifications 2.2.3.1.5. Soft CDR Mode High-Speed I/O Specifications 2.2.3.1.6. Non DPA Mode High-Speed I/O Specifications
2.3. Configuration Specification x
2.3.1. POR Specifications 2.3.2. JTAG Configuration Specifications 2.3.3. Fast Passive Parallel (FPP) Configuration Timing 2.3.4. Active Serial Configuration Timing 2.3.5. Passive Serial Configuration Timing 2.3.6. Initialization 2.3.7. Configuration Files 2.3.8. Remote System Upgrades Circuitry Timing Specification 2.3.9. User Watchdog Internal Oscillator Frequency Specification
2.3.3. Fast Passive Parallel (FPP) Configuration Timing x
2.3.3.1. DCLK-to-DATA[] Ratio (r) for FPP Configuration 2.3.3.2. FPP Configuration Timing when DCLK to DATA[] = 1 2.3.3.3. FPP Configuration Timing when DCLK to DATA[] > 1
2.4. I/O Timing x
2.4.1. Programmable IOE Delay 2.4.2. Programmable Output Buffer Delay
1. Arria® V GX, GT, SX, and ST Device Datasheet
2. Arria V GZ Device Datasheet

1.2.1.2. Transceiver Specifications for Arria V GT and ST Devices

Table 26.  Reference Clock Specifications for Arria® V GT and ST Devices
Symbol/Description Condition Transceiver Speed Grade 3 Unit
Min Typ Max
Supported I/O standards 1.2 V PCML, 1.4 VPCML, 1.5 V PCML, 2.5 V PCML, Differential LVPECL40, HCSL, and LVDS
Input frequency from REFCLK input pins — 27 — 710 MHz
Rise time Measure at ±60 mV of differential signal 41 — — 400 ps
Fall time Measure at ±60 mV of differential signal41 — — 400 ps
Duty cycle — 45 — 55 %
Peak-to-peak differential input voltage — 200 — 30042/2000 mV
Spread-spectrum modulating clock frequency PCIe* 30 — 33 kHz
Spread-spectrum downspread PCIe* — 0 to –0.5% — —
On-chip termination resistors — — 100 — Ω
VICM (AC coupled) — — 1.2 — V
VICM (DC coupled) HCSL I/O standard for the PCIe* reference clock 250 — 550 mV
Transmitter REFCLK phase noise43 10 Hz — — –50 dBc/Hz
100 Hz — — –80 dBc/Hz
1 KHz — — –110 dBc/Hz
10 KHz — — –120 dBc/Hz
100 KHz — — –120 dBc/Hz
≥ 1 MHz — — –130 dBc/Hz
RREF — — 2000 ±1% — Ω
Table 27.  Transceiver Clocks Specifications for Arria® V GT and ST Devices
Symbol/Description Condition Transceiver Speed Grade 3 Unit
Min Typ Max
fixedclk clock frequency PCIe* Receiver Detect — 125 — MHz
Transceiver Reconfiguration Controller Intel® FPGA IP (mgmt_clk_clk) clock frequency — 75 — 125 MHz
Table 28.  Receiver Specifications for Arria® V GT and ST Devices
Symbol/Description Condition Transceiver Speed Grade 3 Unit
Min Typ Max
Supported I/O Standards 1.5 V PCML, 2.5 V PCML, LVPECL, and LVDS
Data rate (6-Gbps transceiver) 44 — 611 — 6553.6 Mbps
Data rate (10-Gbps transceiver)44 — 0.611 — 10.3125 Gbps
Absolute VMAX for a receiver pin45 — — — 1.35 V
Absolute VMIN for a receiver pin — –0.4 — — V
Maximum peak-to-peak differential input voltage VID (diff p-p) before device configuration — — — 1.6 V
Maximum peak-to-peak differential input voltage VID (diff p-p) after device configuration — — — 2.2 V
Minimum differential eye opening at the receiver serial input pins46 — 100 — — mV
VICM (AC coupled) — — 75047/800 — mV
VICM (DC coupled) ≤ 3.2Gbps 48 670 700 730 mV
Differential on-chip termination resistors 85-Ω setting 85 Ω
100-Ω setting 100 Ω
120-Ω setting 120 Ω
150-Ω setting 150 Ω
tLTR 49 — — — 10 µs
tLTD 50 — 4 — — µs
tLTD_manual 51 — 4 — — µs
tLTR_LTD_manual 52 — 15 — — µs
Programmable ppm detector53 — ±62.5, 100, 125, 200, 250, 300, 500, and 1000 ppm
Run length — — — 200 UI
Programmable equalization AC and DC gain

AC gain setting = 0 to 354

DC gain setting = 0 to 1

Refer to CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain for Arria® V GX, GT, SX, and ST Devices and CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain for Arria® V GX, GT, SX, and ST Devices diagrams.
Table 29.  Transmitter Specifications for Arria® V GT and ST Devices
Symbol/Description Condition Transceiver Speed Grade 3 Unit
Min Typ Max
Supported I/O standards 1.5 V PCML
Data rate (6-Gbps transceiver) — 611 — 6553.6 Mbps
Data rate (10-Gbps transceiver) — 0.611 — 10.3125 Gbps
VOCM (AC coupled) — — 650 — mV
VOCM (DC coupled) ≤ 3.2 Gbps48 670 700 730 mV
Differential on-chip termination resistors 85-Ω setting — 85 — Ω
100-Ω setting — 100 — Ω
120-Ω setting — 120 — Ω
150-Ω setting — 150 — Ω
Intra-differential pair skew TX VCM = 0.65 V (AC coupled) and slew rate of 15 ps — — 15 ps
Intra-transceiver block transmitter channel-to-channel skew ×6 PMA bonded mode — — 180 ps
Inter-transceiver block transmitter channel-to-channel skew55 ×N PMA bonded mode — — 500 ps
Table 30.  CMU PLL Specifications for Arria® V GT and ST Devices
Symbol/Description Transceiver Speed Grade 3 Unit
Min Max
Supported data range 0.611 10.3125 Gbps
fPLL supported data range 611 3125 Mbps
Table 31.  Transceiver-FPGA Fabric Interface Specifications for Arria® V GT and ST Devices
Symbol/Description Transceiver Speed Grade 3 Unit
Min Max
Interface speed (PMA direct mode) 50 153.656, 16157 MHz
Interface speed (single-width mode) 25 187.5 MHz
Interface speed (double-width mode) 25 163.84 MHz
Related Information
40 Differential LVPECL signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this table.
41 REFCLK performance requires to meet transmitter REFCLK phase noise specification.
42 The maximum peak-to peak differential input voltage of 300 mV is allowed for DC coupled link.
43 The transmitter REFCLK phase jitter is 30 ps p-p (5 ps RMS) with bit error rate (BER) 10-12, equivalent to 14 sigma.
44 To support data rates lower than the minimum specification through oversampling, use the CDR in LTR mode only.
45 The device cannot tolerate prolonged operation at this absolute maximum.
46 The differential eye opening specification at the receiver input pins assumes that you have disabled the Receiver Equalization feature. If you enable the Receiver Equalization feature, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.
47 The AC coupled VICM is 750 mV for PCIe* mode only.
48 For standard protocol compliance, use AC coupling.
49 tLTR is the time required for the receive CDR to lock to the input reference clock frequency after coming out of reset.
50 tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high.
51 tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high when the CDR is functioning in the manual mode.
52 tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtoref signal goes high when the CDR is functioning in the manual mode.
53 The rate match FIFO supports only up to ±300 ppm.
54 The Intel® Quartus® Prime software allows AC gain setting = 3 for design with data rate between 611 Mbps and 1.25 Gbps only.
55 This specification is only applicable to channels on one side of the device across two transceiver banks.
56 The maximum frequency when core transceiver local routing is selected.
57 The maximum frequency when core transceiver network routing (GCLK, RCLK, or PCLK) is selected.
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