Arria® V Device Datasheet

ID 683022
Date 5/23/2023
Document Table of Contents

1.3.2. FPGA JTAG Configuration Timing

Table 64.  FPGA JTAG Timing Parameters and Values for Arria® V Devices
Symbol Description Min Max Unit
tJCP TCK clock period 30, 16793 ns
tJCH TCK clock high time 14 ns
tJCL TCK clock low time 14 ns
tJPSU (TDI) TDI JTAG port setup time 2 ns
tJPSU (TMS) TMS JTAG port setup time 3 ns
tJPH JTAG port hold time 5 ns
tJPCO JTAG port clock to output 12 94 ns
tJPZX JTAG port high impedance to valid output 1494 ns
tJPXZ JTAG port valid output to high impedance 1494 ns
93 The minimum TCK clock period is 167 ns if VCCBAT is within the range 1.2 V – 1.5 V when you perform the volatile key programming.
94 A 1-ns adder is required for each VCCIO voltage step down from 3.0 V. For example, tJPCO= 13 ns if VCCIO of the TDO I/O bank = 2.5 V, or 14 ns if it equals 1.8 V.

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