Arria® V Device Datasheet

ID 683022
Date 5/23/2023
Public
Document Table of Contents

2.2.1.3. Receiver

Table 102.  Receiver Specifications for Arria V GZ DevicesSpeed grades shown refer to the PMA Speed Grade in the device ordering code. The maximum data rate could be restricted by the Core/PCS speed grade. Contact your Intel Sales Representative for the maximum data rate specifications in each speed grade combination offered. For more information about device ordering codes, refer to the Arria V Device Overview.
Symbol/Description Conditions Transceiver Speed Grade 2 Transceiver Speed Grade 3 Unit
Min Typ Max Min Typ Max
Supported I/O Standards 1.4-V PCML, 1.5-V PCML, 2.5-V PCML, LVPECL, and LVDS
Data rate (Standard PCS) 146, 147 600 9900 600 8800 Mbps
Data rate (10G PCS) 146, 147 600 12500 600 10312.5 Mbps
Absolute VMAX for a receiver pin 148 1.2 1.2 V
Absolute VMIN for a receiver pin –0.4 –0.4 V
Maximum peak-to-peak differential input voltage VID (diff p-p) before device configuration 1.6 1.6 V
Maximum peak-to-peak differential input voltage VID (diff p-p) after device configuration 149 VCCR_GXB = 1.0 V 
(VICM = 0.75 V) 1.8 1.8 V
VCCR_GXB = 0.85 V
(VICM = 0.6 V) 2.4 2.4 V
Minimum differential eye opening at receiver serial input pins 150 151 85 85 mV
Differential on-chip termination resistors 85−Ω setting 85 ± 30% 85 ± 30% Ω
100−Ω setting 100 ± 30% 100 ± 30% Ω
120−Ω setting 120 ± 30% 120 ± 30% Ω
150−Ω setting 150 ± 30% 150 ± 30% Ω
VICM (AC and DC coupled) VCCR_GXB = 0.85 V
full bandwidth 600 600 mV
VCCR_GXB = 0.85 V
half bandwidth 600 600 mV
VCCR_GXB = 1.0 V
full bandwidth 700 700 mV
VCCR_GXB = 1.0 V
half bandwidth 700 700 mV
tLTR 152 10 10 µs
tLTD 153 4 4 µs
tLTD_manual 154 4 4 µs
tLTR_LTD_manual 155 15 15 µs
Programmable equalization
(AC Gain) Full bandwidth (6.25 GHz)

Half bandwidth (3.125 GHz)

16 16 dB
Programmable DC gain DC gain setting = 0 0 0 dB
DC gain setting = 1 2 2 dB
DC gain setting = 2 4 4 dB
DC gain setting = 3 6 6 dB
DC gain setting = 4 8 8 dB
146 The line data rate may be limited by PCS-FPGA interface speed grade.
147 To support data rates lower than the minimum specification through oversampling, use the CDR in LTR mode only.
148 The device cannot tolerate prolonged operation at this absolute maximum.
149 The maximum peak to peak differential input voltage VID after device configuration is equal to 4 × (absolute VMAX for receiver pin - VICM).
150 The differential eye opening specification at the receiver input pins assumes that Receiver Equalization is disabled. If you enable Receiver Equalization, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.
151 Minimum eye opening of 85 mV is only for the unstressed input eye condition.
152 tLTR is the time required for the receive CDR to lock to the input reference clock frequency after coming out of reset.
153 tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high.
154 tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high when the CDR is functioning in the manual mode.
155 tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtoref signal goes high when the CDR is functioning in the manual mode.

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