Arria® V Device Datasheet

ID 683022
Date 5/23/2023
Document Table of Contents HPS JTAG Timing Specifications

Table 62.  HPS JTAG Timing Parameters and Values for Arria® V Devices
Symbol Description Min Max Unit
tJCP TCK clock period 30 ns
tJCH TCK clock high time 14 ns
tJCL TCK clock low time 14 ns
tJPSU (TDI) TDI JTAG port setup time 2 ns
tJPSU (TMS) TMS JTAG port setup time 3 ns
tJPH JTAG port hold time 5 ns
tJPCO JTAG port clock to output 12 91 ns
tJPZX JTAG port high impedance to valid output 1491 ns
tJPXZ JTAG port valid output to high impedance 1491 ns
91 A 1-ns adder is required for each VCCIO _HPS voltage step down from 3.0 V. For example, tJPCO= 13 ns if VCCIO _HPS of the TDO I/O bank = 2.5 V, or 14 ns if it equals 1.8 V.