Arria® V Device Datasheet

ID 683022
Date 5/23/2023
Document Table of Contents DPA Mode High-Speed I/O Specifications

Table 120.  High-Speed I/O Specifications for Arria V GZ Devices

When J = 3 to 10, use the serializer/deserializer (SERDES) block.

When J = 1 or 2, bypass the SERDES block.

Symbol Conditions C3, I3L C4, I4 Unit
Min Typ Max Min Typ Max
DPA run length 10000 10000 UI
Figure 25. DPA Lock Time Specification with DPA PLL Calibration Enabled
Table 121.  DPA Lock Time Specifications for Arria V GZ Devices

The DPA lock time is for one channel.

One data transition is defined as a 0-to-1 or 1-to-0 transition.

The DPA lock time stated in this table applies to both commercial and industrial grade.

Standard Training Pattern Number of Data Transitions in One Repetition of the Training Pattern Number of Repetitions per 256 Data Transitions 205 Maximum
SPI-4 00000000001111111111 2 128 640 data transitions
Parallel Rapid I/O 00001111 2 128 640 data transitions
10010000 4 64 640 data transitions
Miscellaneous 10101010 8 32 640 data transitions
01010101 8 32 640 data transitions
205 This is the number of repetitions for the stated training pattern to achieve the 256 data transitions.

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