Arria® V Device Datasheet

ID 683022
Date 5/23/2023
Document Table of Contents ATX PLL

Table 105.  ATX PLL Specifications for Arria V GZ DevicesSpeed grades shown refer to the PMA Speed Grade in the device ordering code. The maximum data rate could be restricted by the Core/PCS speed grade. Contact your Intel Sales Representative for the maximum data rate specifications in each speed grade combination offered. For more information about device ordering codes, refer to the Arria V Device Overview.
Symbol/Description Conditions Transceiver Speed Grade 2 Transceiver Speed Grade 3 Unit
Min Typ Max Min Typ Max
Supported data rate range VCO post-divider
L = 2 8000 12500 8000 10312.5 Mbps
L = 4 4000 6600 4000 6600 Mbps
L = 8 158 2000 3300 2000 3300 Mbps
tpll_powerdown 159 1 1 µs
tpll_lock 160 10 10 µs
158 This clock can be further divided by central or local clock dividers making it possible to use ATX PLL for data rates < 1 Gbps. For more information about ATX PLLs, refer to the Transceiver Clocking in Arria V Devices chapter and the Dynamic Reconfiguration in Arria V Devices chapter.
159 tpll_powerdown is the PLL powerdown minimum pulse width.
160 tpll_lock is the time required for the transmitter CMU/ATX PLL to lock to the input reference clock frequency after coming out of reset.

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