Arria® V Device Datasheet

ID 683022
Date 5/23/2023
Document Table of Contents Memory Output Clock Jitter Specifications

Table 45.  Memory Output Clock Jitter Specifications for Arria® V Devices

The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC* DDR2/DDR3 SDRAM standard.

The memory output clock jitter is applicable when an input jitter of 30 ps (p-p) is applied with bit error rate (BER) 10–12, equivalent to 14 sigma.

Intel recommends using the UniPHY IP cores with PHYCLK connections for better jitter performance.

Parameter Clock Network Symbol –I3, –C4 –I5, –C5 –C6 Unit
Min Max Min Max Min Max
Clock period jitter PHYCLK tJIT(per) –41 41 –50 50 –55 55 ps
Cycle-to-cycle period jitter PHYCLK tJIT(cc) 63 90 94 ps