18.104.22.168.3. HPS PLL Input Jitter
Use the following equation to determine the maximum input jitter (peak-to-peak) the HPS PLLs can tolerate. The divide value (N) is the value programmed into the denominator field of the VCO register for each PLL. The PLL input reference clock is divided by this value. The range of the denominator is 1 to 64.
Maximum input jitter = Input clock period × Divide value (N) × 0.02
|Input Reference Clock Period||Divide Value (N)||Maximum Jitter||Unit|
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