Arria® V Device Datasheet

ID 683022
Date 5/23/2023
Document Table of Contents HPS PLL Input Jitter

Use the following equation to determine the maximum input jitter (peak-to-peak) the HPS PLLs can tolerate. The divide value (N) is the value programmed into the denominator field of the VCO register for each PLL. The PLL input reference clock is divided by this value. The range of the denominator is 1 to 64.

Maximum input jitter = Input clock period × Divide value (N) × 0.02

Table 50.  Examples of Maximum Input Jitter
Input Reference Clock Period Divide Value (N) Maximum Jitter Unit
40 ns 1 0.8 ns
40 ns 2 1.6 ns
40 ns 4 3.2 ns

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