Arria® V Device Datasheet

ID 683022
Date 5/23/2023
Document Table of Contents I2C Timing Characteristics

Table 59.  I2C Timing Requirements for Arria® V Devices
Symbol Description Standard Mode Fast Mode Unit
Min Max Min Max
Tclk Serial clock (SCL) clock period 10 2.5 µs
Tclkhigh SCL high time 4.7 0.6 µs
Tclklow SCL low time 4 1.3 µs
Ts Setup time for serial data line (SDA) data to SCL 0.25 0.1 µs
Th Hold time for SCL to SDA data 0 3.45 0 0.9 µs
Td SCL to SDA output data delay 0.2 0.2 µs
Tsu_start Setup time for a repeated start condition 4.7 0.6 µs
Thd_start Hold time for a repeated start condition 4 0.6 µs
Tsu_stop Setup time for a stop condition 4 0.6 µs
Figure 17. I2C Timing Diagram