PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs

ID 821801
Date 8/29/2025
Public
Document Table of Contents

6.5.3. VREF_CA/RESET Signal Routing Guidelines for Memory Down Topologies

The target impedance for the reset signal is 50 Ω. The reset signal shall have at least 3×h (where h represents trace to nearest reference plane height or distance) spacing to other nearby signals on the same layer. The end-to-end reset trace length is not limited but shall not exceed more than five inches to the first DRAM. Altera recommends using 1.0KΩ pull-down resistor for reset termination.

Figure 69. Reset Scheme and Setting for Memory Down (Discrete) TopologyThis figure shows the reset routing scheme and setting, which you can apply to both single rank and dual-rank memory down topologies
Figure 70. VREF_CA Scheme and Setting for Memory Down (Discrete) TopologyThis figure shows a VREF_CA routing scheme and setting, which you can apply to both single rank and dual-rank memory down topologies.

Altera recommends that you use at least a 10 mil trace width for VREF_CA routing on the PCB. The VREF_CA signal should have at least 3×h (where h represents trace to nearest reference plane height or distance) spacing to other nearby signals on the same layer. The 1.8 KΩ voltage divider circuitry shall be replaced by a 0.9 KΩ resistor, pulled up to 0.6 V from the voltage regulator.