PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs

ID 821801
Date 8/29/2025
Public
Document Table of Contents

6.1.1. FPGA DDR Break Out Routing

Agilex™ 5 devices come with various pitch sizes for different FPGA pins. For VPBGA package devices breakout, Altera recommends you use a dog-bone configuration, stripline routing for inner GPIO pins fan out and microstrip routing for GPIO pins at edge of the device, as suggested in General VPBGA PCB Layout Guideline section. This section provides stripline and microstrip routing guidelines for all supported EMIF interfaces and topologies.

DQS and CLK signals in the DDR interface are differential signals. Altera recommends routing DQS/CLK as differential signals and use a symmetrical fan out at the FPGA pin field.

Figure 54. Symmetrical Routing of Differential Signals (DQS/CLK) at FPGA Pin FieldThis figure shows the symmetrical routing of differential signals (DQS/CLK) at FPGA pin field and the length/skew matching between P and N lanes.