PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs
ID
821801
Date
8/29/2025
Public
1. Overview
2. BGA Footprint and Land Pattern
3. General PCB Design Considerations
4. VPBGA PCB Routing Guidelines
5. MBGA PCB Routing Guidelines
6. EMIF PCB Routing Guidelines (VPBGA and MBGA)
7. MIPI Interface Layout Design Guidelines (VPBGA and MBGA)
8. True Differential I/O Interface PCB Routing Guidelines (VPBGA and MBGA)
9. Power Distribution Network Design Guidelines
10. Document Revision History for the PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs
9.1. Agilex™ 5 Power Distribution Network Design Guidelines Overview
9.2. Power Delivery Overview
9.3. Board Power Delivery Network Recommendations
9.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails
9.5. PCB PDN Design Guideline for Unused GTS Transceiver
9.6. PCB Voltage Regulator Recommendation for PCB Power Rails
9.7. Board PDN Simulations
9.8. Agilex™ 5 Device Family PDN Design Summary
6.1.1. FPGA DDR Break Out Routing
Agilex™ 5 devices come with various pitch sizes for different FPGA pins. For VPBGA package devices breakout, Altera recommends you use a dog-bone configuration, stripline routing for inner GPIO pins fan out and microstrip routing for GPIO pins at edge of the device, as suggested in General VPBGA PCB Layout Guideline section. This section provides stripline and microstrip routing guidelines for all supported EMIF interfaces and topologies.
DQS and CLK signals in the DDR interface are differential signals. Altera recommends routing DQS/CLK as differential signals and use a symmetrical fan out at the FPGA pin field.
Figure 54. Symmetrical Routing of Differential Signals (DQS/CLK) at FPGA Pin FieldThis figure shows the symmetrical routing of differential signals (DQS/CLK) at FPGA pin field and the length/skew matching between P and N lanes.