PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs

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ID 821801
Date 8/29/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. BGA Footprint and Land Pattern 3. General PCB Design Considerations 4. VPBGA PCB Routing Guidelines 5. MBGA PCB Routing Guidelines 6. EMIF PCB Routing Guidelines (VPBGA and MBGA) 7. MIPI Interface Layout Design Guidelines (VPBGA and MBGA) 8. True Differential I/O Interface PCB Routing Guidelines (VPBGA and MBGA) 9. Power Distribution Network Design Guidelines 10. Document Revision History for the PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs
1. Overview x
1.1. Agilex™ 5 FPGAs and SoCs Packages
2. BGA Footprint and Land Pattern x
2.1. Metal-Defined Board Pad 2.2. Spoked Pad 2.3. Wide Trace Metal-Defined Pad 2.4. Solder Mask-Defined Pad 2.5. Recommended Land Patterns
3. General PCB Design Considerations x
3.1. Impedance Tolerances 3.2. Reference Planes 3.3. Layer Assignment 3.4. Via Drill Size 3.5. Fiber Weave 3.6. PCB Traces 3.7. PCB Vias 3.8. AC Coupling Capacitors 3.9. Other Considerations
3.6. PCB Traces x
3.6.1. Zig-Zag Routing 3.6.2. Image Rotation
4. VPBGA PCB Routing Guidelines x
4.1. Pin Distribution and Ball Pitches 4.2. Fan-Out and Routing Strategy 4.3. Power Pins 4.4. HSSI Reference PCB Stack-up 4.5. Agilex™ 5 GTS Transceiver 4.6. GTS Transceiver PCIe* 4.0 16 GT/s NRZ Interface Design Guidelines 4.7. GTS Transceiver Ethernet 25G NRZ Interface Design Guidelines
4.5. Agilex™ 5 GTS Transceiver x
4.5.1. HSSI Pin-Field Breakout for VPBGA
4.6. GTS Transceiver PCIe* 4.0 16 GT/s NRZ Interface Design Guidelines x
4.6.1. GTS Transceiver Channel Recommendations 4.6.2. General Guidelines for GTS Transceiver PCIe* Gen 4.0 Interface 4.6.3. PCIe* Add-In Card Edge Finger
4.7. GTS Transceiver Ethernet 25G NRZ Interface Design Guidelines x
4.7.1. GTS Transceiver Channel Recommendations 4.7.2. General Guidelines for GTS Transceiver Ethernet Interface 4.7.3. Quad Small Form-factor Pluggable Connector Routing 4.7.4. Small Form-factor Pluggable (SFP) Connector Routing 4.7.5. Other Connectors
4.7.5. Other Connectors x
4.7.5.1. ADM/F Connectors 4.7.5.2. DP and HDMI Connectors 4.7.5.3. FMC+ Connectors
5. MBGA PCB Routing Guidelines x
5.1. Typical Design Rules for Type-IV HDI in a 0.5 mm MBGA 5.2. HSSI Breakout 5.3. EMIF Breakout
6. EMIF PCB Routing Guidelines (VPBGA and MBGA) x
6.1. General DDR Signal Routing Guideline on PCB 6.2. General Notes for EMIF Routing Guidelines Table 6.3. LPDDR5 Interface Design Guidelines 6.4. LPDDR4 Interface Design Guidelines 6.5. DDR4 Interface Design Guidelines 6.6. LPDDR5, LPDDR4, and DDR4 Simulation Strategy
6.1. General DDR Signal Routing Guideline on PCB x
6.1.1. FPGA DDR Break Out Routing 6.1.2. DRAM Break Out in Layout Routing 6.1.3. Ground Plane and Return Path
6.3. LPDDR5 Interface Design Guidelines x
6.3.1. LPDDR5 Memory Down Topology (Single Rank or Dual-Rank)
6.4. LPDDR4 Interface Design Guidelines x
6.4.1. LPDDR4 Memory Down Topology (Up to 32-bits Interface) 6.4.2. Tables for Comprehensive Routing Guidelines for Each LPDDR4 Signal
6.5. DDR4 Interface Design Guidelines x
6.5.1. Single Rank ×8 Memory Down Topology 6.5.2. Single Rank ×16 Memory Down Topology 6.5.3. VREF_CA/RESET Signal Routing Guidelines for Memory Down Topologies 6.5.4. Skew Matching Guidelines for DDR4 Memory Down Configurations 6.5.5. Power Delivery Recommendation for DDR4 Discrete Configurations
9. Power Distribution Network Design Guidelines x
9.1. Agilex™ 5 Power Distribution Network Design Guidelines Overview 9.2. Power Delivery Overview 9.3. Board Power Delivery Network Recommendations 9.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails 9.5. PCB PDN Design Guideline for Unused GTS Transceiver 9.6. PCB Voltage Regulator Recommendation for PCB Power Rails 9.7. Board PDN Simulations 9.8. Agilex™ 5 Device Family PDN Design Summary
9.1. Agilex™ 5 Power Distribution Network Design Guidelines Overview x
9.1.1. Device Guidelines Status for Agilex™ 5 Devices
9.2. Power Delivery Overview x
9.2.1. Power Architecture 9.2.2. Rail Merger Requirements 9.2.3. Power Rails Specification 9.2.4. Decoupling Capacitors Recommendation
9.2.1. Power Architecture x
9.2.1.1. Power Budget 9.2.1.2. Power Tree
9.2.1.2. Power Tree x
9.2.1.2.1. Recommended Power Tree for SmartVID Devices with GTS Transceiver 9.2.1.2.2. Recommended Power Tree for Non-SmartVID Devices with GTS Transceiver
9.2.3. Power Rails Specification x
9.2.3.1. Power Nets 9.2.3.2. Power Rails Tolerance 9.2.3.3. Power Nets and Transient Specifications
9.2.3.1. Power Nets x
9.2.3.1.1. Agilex™ 5 Package Power Nets and Subsystems Details
9.2.4. Decoupling Capacitors Recommendation x
9.2.4.1. Agilex™ 5 FPGA Packages Board-Level Decoupling Capacitors Summary 9.2.4.2. Agilex™ 5 GTS Transceiver Board-Level Decoupling Capacitors Summary
9.3. Board Power Delivery Network Recommendations x
9.3.1. Board Decoupling Capacitors Guide 9.3.2. FPGA Core Fabric VCC Voltage Regulator Selection 9.3.3. Remote Sense Connections 9.3.4. Load Line Requirements 9.3.5. VCC Core Board Current Slew Rate
9.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails x
Choosing the LC Filter Based on the DCR Value VCCBAT RC Circuit Using the Device Security AES BBRAM Key P0V8 (VCCL or P0V8_GR1) Filters Recommendation for Device Fabric P1V8_GR2a Filters Recommendation for Device Fabric 9.4.1. GTS Transceiver Rail Board Connection and LC Filter Recommendation Under Noisy Voltage Regulator
9.5. PCB PDN Design Guideline for Unused GTS Transceiver x
9.5.1. PDN Design Guideline for Unused GTS Transceiver
1. Overview
2. BGA Footprint and Land Pattern
3. General PCB Design Considerations
4. VPBGA PCB Routing Guidelines
5. MBGA PCB Routing Guidelines
6. EMIF PCB Routing Guidelines (VPBGA and MBGA)
7. MIPI Interface Layout Design Guidelines (VPBGA and MBGA)
8. True Differential I/O Interface PCB Routing Guidelines (VPBGA and MBGA)
9. Power Distribution Network Design Guidelines
10. Document Revision History for the PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs

9.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails

The part numbers of ferrite bead (FB) and inductances (L) selected in this chapter are recommended by Altera. You can select different parts provided their inductance/impedance, resistance, and other parameters are similar to the recommended components. Ensure they have comparable inductance or impedance values at certain frequency and lower DCR within the specified frequency range stated in the data sheet..

CAUTION:
You must place any sense line on board before the LC filter. Placing the sense lines after the LC filter causes a serious oscillation to the rails and unstable voltage that is an input to the voltage regulator feedback pin function.
Note: If the power rail is using LDO, you do not need to use the LC filter.

Provided your design meets the simulated ripple specification of 5 mV using the recommended switching voltage regulator (LTC7151S), you do not need to use the LC filter for the VCCERT_GTS and VCCEHT_GTS rails.

Table 29.   Recommended Inductors and Ferrite Beads for the LC Filter
Manufacturing Part Number (MPN) L (nH) DCR (mΩ)
BLM18SN220TZ1 — 4
BLM18KG260TN1 — 7

Altera has validated the inductors or ferrite beads on Altera development kits and are for reference only. You can select other inductors or ferrite beads according to specific applications, as long as the preceding specification stated can be met and the LC filter works well. Altera recommends running the simulation to verify expected functionality.

Table 30.   Recommended Capacitors Used for the LC Filter
Manufacturing Part Number (MPN) Size (mm/inch) Temperature Characteristics C (µF) Tolerance (%) Rated Voltage (V)
GRM21BC80G107ME15 2012M/0805 X6S 100 ±20 4
GRM188C80G476ME01 1608M/0603 X6S 47 ±20 4

The capacitors in the table have been validated on Altera development kits and are for reference only. You can choose other capacitors according to specific applications, with different package size, temperature range, form factor, and rated voltage, as long as the preceding specification stated can be met and the LC Filter works well. Altera recommends running the simulation to verify expected functionality.

Choosing the LC Filter Based on the DCR Value

DC drop specification must be around 0.5% of the voltage supply. If the voltage rail is 0.9 V, current is 1 A, BLM18SN220TZ1 DCR is 4 mΩ, DC drop = current x DCR = 1 A x 4 mΩ = 4 mV. The 0.5% specification of 0.9 V is 4.5 mV, so 4 mV is within the specification. For a higher current value, SL1616 is the most suitable as it has lowest DCR.

VCCBAT RC Circuit Using the Device Security AES BBRAM Key

The connection shown below is recommended for VCCBAT. Connect this pin to a non-volatile battery power source in the range of 1.0 V to 1.8 V. A series RC (R = 10 KΩ, C = 1 µF) circuit must be added to the VCCBAT rail.

Figure 79. VCCBAT Rail RC Circuit Recommendation

P0V8 (VCCL or P0V8_GR1) Filters Recommendation for Device Fabric

The following figure shows the filter recommendation for VCCPLLDIG1_HPS, VCCPLLDIG2_HPS, and VCCPLLDIG_SDM in 0.8 V group 1 power rail.

Figure 80. VCCPLLDIG1_HPS and VCCPLLDIG2_HPS LC Filter Recommendation
Figure 81. VCCPLLDIG_SDM LC Filter Recommendation

P1V8_GR2a Filters Recommendation for Device Fabric

The connections below are recommended for the VCCPLL1_HPS, VCCPLL2_HPS, VCCADC, and VCCPLL_SDM LC filter to the P1V8_GR2a voltage rails for Agilex™ 5 devices.

You can design the filter by combining or splitting these four power rails depends on PCB routing.

Figure 82. VCCPLL1_HPS and VCCPLL2_HPS LC Filter Recommendation
Figure 83. VCCADC and VCCPLL_SDM LC Filter Recommendation

Section Content
GTS Transceiver Rail Board Connection and LC Filter Recommendation Under Noisy Voltage Regulator

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