PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs
ID
821801
Date
8/29/2025
Public
1. Overview
2. BGA Footprint and Land Pattern
3. General PCB Design Considerations
4. VPBGA PCB Routing Guidelines
5. MBGA PCB Routing Guidelines
6. EMIF PCB Routing Guidelines (VPBGA and MBGA)
7. MIPI Interface Layout Design Guidelines (VPBGA and MBGA)
8. True Differential I/O Interface PCB Routing Guidelines (VPBGA and MBGA)
9. Power Distribution Network Design Guidelines
10. Document Revision History for the PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs
9.1. Agilex™ 5 Power Distribution Network Design Guidelines Overview
9.2. Power Delivery Overview
9.3. Board Power Delivery Network Recommendations
9.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails
9.5. PCB PDN Design Guideline for Unused GTS Transceiver
9.6. PCB Voltage Regulator Recommendation for PCB Power Rails
9.7. Board PDN Simulations
9.8. Agilex™ 5 Device Family PDN Design Summary
4.3. Power Pins
The power pins for Agilex™ 5 VPBGA devices are mainly located in the center BGA area, with some GPIO pins at the edge of the center BGA areas to ease the signal trace routing as shown in the Power and Ground Pins at the VPBGA Package Center Area figure. You can find the current values and other relevant specifications for each power rail in the Power Distribution Network Design Guidelines section. Altera recommends following the requirements in the PDN design guidelines. DC IR drop and PDN transient simulations during the post layout simulation stage are helpful for the design. For a lower inductance connection, it is advisable for power vias to have a solid and unbroken connection to the power planes.
Figure 21. Power and Ground Pins at the VPBGA Package Center AreaThis figure shows the fan-out strategy in Agilex™ 5 VPBGA devices.