PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs

ID 821801
Date 8/29/2025
Public
Document Table of Contents

4.3. Power Pins

The power pins for Agilex™ 5 VPBGA devices are mainly located in the center BGA area, with some GPIO pins at the edge of the center BGA areas to ease the signal trace routing as shown in the Power and Ground Pins at the VPBGA Package Center Area figure. You can find the current values and other relevant specifications for each power rail in the Power Distribution Network Design Guidelines section. Altera recommends following the requirements in the PDN design guidelines. DC IR drop and PDN transient simulations during the post layout simulation stage are helpful for the design. For a lower inductance connection, it is advisable for power vias to have a solid and unbroken connection to the power planes.

Figure 21. Power and Ground Pins at the VPBGA Package Center AreaThis figure shows the fan-out strategy in Agilex™ 5 VPBGA devices.