PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs
ID
821801
Date
8/29/2025
Public
1. Overview
2. BGA Footprint and Land Pattern
3. General PCB Design Considerations
4. VPBGA PCB Routing Guidelines
5. MBGA PCB Routing Guidelines
6. EMIF PCB Routing Guidelines (VPBGA and MBGA)
7. MIPI Interface Layout Design Guidelines (VPBGA and MBGA)
8. True Differential I/O Interface PCB Routing Guidelines (VPBGA and MBGA)
9. Power Distribution Network Design Guidelines
10. Document Revision History for the PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs
9.1. Agilex™ 5 Power Distribution Network Design Guidelines Overview
9.2. Power Delivery Overview
9.3. Board Power Delivery Network Recommendations
9.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails
9.5. PCB PDN Design Guideline for Unused GTS Transceiver
9.6. PCB Voltage Regulator Recommendation for PCB Power Rails
9.7. Board PDN Simulations
9.8. Agilex™ 5 Device Family PDN Design Summary
4.7.1. GTS Transceiver Channel Recommendations
- Maximum 1.2 inches of PCB route length on SoM and 2.2 inches on the carrier board. Evaluate the maximum routing length based on specific PCB stack-up and standards.
- Follow the pair-to-pair spacing rules:
- Keep the insertion loss within the requirement of IEEE specification.
- Make the N/P routing as symmetrical as possible.
- Ensure that the ground plane fully surrounds the HSSI traces.
Informative
- Target Differential Impedance: 90 Ω on SoM and carrier board (95 Ω or 100 Ω is also possible depends on PCB stack-up design).
- Differential return loss lower than -15 dB from 0 to Nyquist frequency (depends on specific data rate).
3 'H' is the distance from the signal layer to the closest reference layer