PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs
4.7.3. Quad Small Form-factor Pluggable Connector Routing
To minimize the inductance of the ground connection, add ground vias on both sides of the connector ground pins and connect them with a short and thick ground trace. Keep the connector ground pins locally-shorted to maintain an equal potential.
Length matching for each pair is required. Both P and N lanes must be in phase to recover the data.
For breakout design, refer to the following figure.
To minimize insertion loss, always use the minimum routing length from the FPGA to the connector.
Altera recommends using a 3D simulation to optimize the BGA breakout.
Try keeping the return loss lower than –15 dB at the Nyquist frequency, preferably lower than –20 dB.
Control the impedance variation of the cut out area by making the cut-out as small as possible, ideally within ±5 Ω.