PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs

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ID 821801
Date 8/29/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. BGA Footprint and Land Pattern 3. General PCB Design Considerations 4. VPBGA PCB Routing Guidelines 5. MBGA PCB Routing Guidelines 6. EMIF PCB Routing Guidelines (VPBGA and MBGA) 7. MIPI Interface Layout Design Guidelines (VPBGA and MBGA) 8. True Differential I/O Interface PCB Routing Guidelines (VPBGA and MBGA) 9. Power Distribution Network Design Guidelines 10. Document Revision History for the PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs
1. Overview x
1.1. Agilex™ 5 FPGAs and SoCs Packages
2. BGA Footprint and Land Pattern x
2.1. Metal-Defined Board Pad 2.2. Spoked Pad 2.3. Wide Trace Metal-Defined Pad 2.4. Solder Mask-Defined Pad 2.5. Recommended Land Patterns
3. General PCB Design Considerations x
3.1. Impedance Tolerances 3.2. Reference Planes 3.3. Layer Assignment 3.4. Via Drill Size 3.5. Fiber Weave 3.6. PCB Traces 3.7. PCB Vias 3.8. AC Coupling Capacitors 3.9. Other Considerations
3.6. PCB Traces x
3.6.1. Zig-Zag Routing 3.6.2. Image Rotation
4. VPBGA PCB Routing Guidelines x
4.1. Pin Distribution and Ball Pitches 4.2. Fan-Out and Routing Strategy 4.3. Power Pins 4.4. HSSI Reference PCB Stack-up 4.5. Agilex™ 5 GTS Transceiver 4.6. GTS Transceiver PCIe* 4.0 16 GT/s NRZ Interface Design Guidelines 4.7. GTS Transceiver Ethernet 25G NRZ Interface Design Guidelines
4.5. Agilex™ 5 GTS Transceiver x
4.5.1. HSSI Pin-Field Breakout for VPBGA
4.6. GTS Transceiver PCIe* 4.0 16 GT/s NRZ Interface Design Guidelines x
4.6.1. GTS Transceiver Channel Recommendations 4.6.2. General Guidelines for GTS Transceiver PCIe* Gen 4.0 Interface 4.6.3. PCIe* Add-In Card Edge Finger
4.7. GTS Transceiver Ethernet 25G NRZ Interface Design Guidelines x
4.7.1. GTS Transceiver Channel Recommendations 4.7.2. General Guidelines for GTS Transceiver Ethernet Interface 4.7.3. Quad Small Form-factor Pluggable Connector Routing 4.7.4. Small Form-factor Pluggable (SFP) Connector Routing 4.7.5. Other Connectors
4.7.5. Other Connectors x
4.7.5.1. ADM/F Connectors 4.7.5.2. DP and HDMI Connectors 4.7.5.3. FMC+ Connectors
5. MBGA PCB Routing Guidelines x
5.1. Typical Design Rules for Type-IV HDI in a 0.5 mm MBGA 5.2. HSSI Breakout 5.3. EMIF Breakout
6. EMIF PCB Routing Guidelines (VPBGA and MBGA) x
6.1. General DDR Signal Routing Guideline on PCB 6.2. General Notes for EMIF Routing Guidelines Table 6.3. LPDDR5 Interface Design Guidelines 6.4. LPDDR4 Interface Design Guidelines 6.5. DDR4 Interface Design Guidelines 6.6. LPDDR5, LPDDR4, and DDR4 Simulation Strategy
6.1. General DDR Signal Routing Guideline on PCB x
6.1.1. FPGA DDR Break Out Routing 6.1.2. DRAM Break Out in Layout Routing 6.1.3. Ground Plane and Return Path
6.3. LPDDR5 Interface Design Guidelines x
6.3.1. LPDDR5 Memory Down Topology (Single Rank or Dual-Rank)
6.4. LPDDR4 Interface Design Guidelines x
6.4.1. LPDDR4 Memory Down Topology (Up to 32-bits Interface) 6.4.2. Tables for Comprehensive Routing Guidelines for Each LPDDR4 Signal
6.5. DDR4 Interface Design Guidelines x
6.5.1. Single Rank ×8 Memory Down Topology 6.5.2. Single Rank ×16 Memory Down Topology 6.5.3. VREF_CA/RESET Signal Routing Guidelines for Memory Down Topologies 6.5.4. Skew Matching Guidelines for DDR4 Memory Down Configurations 6.5.5. Power Delivery Recommendation for DDR4 Discrete Configurations
9. Power Distribution Network Design Guidelines x
9.1. Agilex™ 5 Power Distribution Network Design Guidelines Overview 9.2. Power Delivery Overview 9.3. Board Power Delivery Network Recommendations 9.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails 9.5. PCB PDN Design Guideline for Unused GTS Transceiver 9.6. PCB Voltage Regulator Recommendation for PCB Power Rails 9.7. Board PDN Simulations 9.8. Agilex™ 5 Device Family PDN Design Summary
9.1. Agilex™ 5 Power Distribution Network Design Guidelines Overview x
9.1.1. Device Guidelines Status for Agilex™ 5 Devices
9.2. Power Delivery Overview x
9.2.1. Power Architecture 9.2.2. Rail Merger Requirements 9.2.3. Power Rails Specification 9.2.4. Decoupling Capacitors Recommendation
9.2.1. Power Architecture x
9.2.1.1. Power Budget 9.2.1.2. Power Tree
9.2.1.2. Power Tree x
9.2.1.2.1. Recommended Power Tree for SmartVID Devices with GTS Transceiver 9.2.1.2.2. Recommended Power Tree for Non-SmartVID Devices with GTS Transceiver
9.2.3. Power Rails Specification x
9.2.3.1. Power Nets 9.2.3.2. Power Rails Tolerance 9.2.3.3. Power Nets and Transient Specifications
9.2.3.1. Power Nets x
9.2.3.1.1. Agilex™ 5 Package Power Nets and Subsystems Details
9.2.4. Decoupling Capacitors Recommendation x
9.2.4.1. Agilex™ 5 FPGA Packages Board-Level Decoupling Capacitors Summary 9.2.4.2. Agilex™ 5 GTS Transceiver Board-Level Decoupling Capacitors Summary
9.3. Board Power Delivery Network Recommendations x
9.3.1. Board Decoupling Capacitors Guide 9.3.2. FPGA Core Fabric VCC Voltage Regulator Selection 9.3.3. Remote Sense Connections 9.3.4. Load Line Requirements 9.3.5. VCC Core Board Current Slew Rate
9.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails x
9.4.1. GTS Transceiver Rail Board Connection and LC Filter Recommendation Under Noisy Voltage Regulator
9.5. PCB PDN Design Guideline for Unused GTS Transceiver x
9.5.1. PDN Design Guideline for Unused GTS Transceiver
1. Overview
2. BGA Footprint and Land Pattern
3. General PCB Design Considerations
4. VPBGA PCB Routing Guidelines
5. MBGA PCB Routing Guidelines
6. EMIF PCB Routing Guidelines (VPBGA and MBGA)
7. MIPI Interface Layout Design Guidelines (VPBGA and MBGA)
8. True Differential I/O Interface PCB Routing Guidelines (VPBGA and MBGA)
9. Power Distribution Network Design Guidelines
10. Document Revision History for the PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs

4.2. Fan-Out and Routing Strategy

Altera recommends the dog-bone fan out structure for Agilex™ 5 VPBGA devices.

Figure 15. Dog-Bone Fan-Out Structure

To facilitate easy routing, the 0.65 mm ball pitch is optimized to have one signal trace to route through on the top layer as shown in Example Fan-Out for the Two Outermost Rows or Columns in the GPIO Area in the Top Layer figure. Typically, those pins are used as EMIF DQ group and other GPIOs.

Figure 16. Example Fan-Out for the Two Outermost Rows or Columns in the GPIO Area in the Top LayerThis figure shows the fan-out example for Agilex™ 5 VPBGA devices.

In the Example Fan-Out of Inner Layer figure, the GPIO pins are located at the inner area of the BGA. Every two columns of the GPIOs are spaced approximately 1.45 mm apart. Depending on the specific stack-up design, this spacing allows a fan-out of up to five or six signal-ended signals.

Figure 17. Example Fan-Out of Inner LayerThis figure shows an example of a fan-out strategy in Agilex™ 5 VPBGA devices.

To reduce the total layer count, fan out more signals on each layer. Consider implementing vias with 8 mil or 10 mil drill hole size for GPIO pins. Refer to EMIF PCB Routing Guidelines section for detailed recommendations on spacing, length matching, maximum routing length, and others of EMIF signals with microstrip or stripline routing.

For transceiver BGA area, you can consider routing microstrip lines for fan out on the top layer for high-density designs that need fewer PCB layers as shown in the Example Fan-Out for Top Layer with Differential Pairs figure. However, this changes the impedance control tolerance, total insertion loss, crosstalk and others. Hence, Altera recommends conducting simulations to verify especially when implementing long microstrip length.

Figure 18. Example Fan-Out for Top Layer with Differential Pairs

When the outer two rows of transceivers are routed with microstrip at top layer, you can use the differential pair routing in inner layer fan out as shown in Example Fan-Out for Inner Layer with Differential Pairs.

Figure 19. Example Fan-Out for Inner Layer with Differential Pairs

Alternatively, you can also use single-ended traces for inner layer transceiver fan out to meet the drill to metal requirement (D2M, usually 7 to 8 mil) as demonstrated in Example Fan-Out for Inner Layer with Single-Ended Traces figure.

Figure 20. Example Fan-Out for Inner Layer with Single-Ended Traces

For high-speed signal vias, use backdrilling technology to minimize the stub effect. You can find detailed simulation results of the reference design in GTS Transceiver PCIe Gen4 16 GT/s NRZ Interface Design Guidelines and GTS Transceiver Ethernet 25 Gbps NRZ Interface Design Guidelines sections.

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