PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs

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ID 821801
Date 8/29/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. BGA Footprint and Land Pattern 3. General PCB Design Considerations 4. VPBGA PCB Routing Guidelines 5. MBGA PCB Routing Guidelines 6. EMIF PCB Routing Guidelines (VPBGA and MBGA) 7. MIPI Interface Layout Design Guidelines (VPBGA and MBGA) 8. True Differential I/O Interface PCB Routing Guidelines (VPBGA and MBGA) 9. Power Distribution Network Design Guidelines 10. Document Revision History for the PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs
1. Overview x
1.1. Agilex™ 5 FPGAs and SoCs Packages
2. BGA Footprint and Land Pattern x
2.1. Metal-Defined Board Pad 2.2. Spoked Pad 2.3. Wide Trace Metal-Defined Pad 2.4. Solder Mask-Defined Pad 2.5. Recommended Land Patterns
3. General PCB Design Considerations x
3.1. Impedance Tolerances 3.2. Reference Planes 3.3. Layer Assignment 3.4. Via Drill Size 3.5. Fiber Weave 3.6. PCB Traces 3.7. PCB Vias 3.8. AC Coupling Capacitors 3.9. Other Considerations
3.6. PCB Traces x
3.6.1. Zig-Zag Routing 3.6.2. Image Rotation
4. VPBGA PCB Routing Guidelines x
4.1. Pin Distribution and Ball Pitches 4.2. Fan-Out and Routing Strategy 4.3. Power Pins 4.4. HSSI Reference PCB Stack-up 4.5. Agilex™ 5 GTS Transceiver 4.6. GTS Transceiver PCIe* 4.0 16 GT/s NRZ Interface Design Guidelines 4.7. GTS Transceiver Ethernet 25G NRZ Interface Design Guidelines
4.5. Agilex™ 5 GTS Transceiver x
4.5.1. HSSI Pin-Field Breakout for VPBGA
4.6. GTS Transceiver PCIe* 4.0 16 GT/s NRZ Interface Design Guidelines x
4.6.1. GTS Transceiver Channel Recommendations 4.6.2. General Guidelines for GTS Transceiver PCIe* Gen 4.0 Interface 4.6.3. PCIe* Add-In Card Edge Finger
4.7. GTS Transceiver Ethernet 25G NRZ Interface Design Guidelines x
4.7.1. GTS Transceiver Channel Recommendations 4.7.2. General Guidelines for GTS Transceiver Ethernet Interface 4.7.3. Quad Small Form-factor Pluggable Connector Routing 4.7.4. Small Form-factor Pluggable (SFP) Connector Routing 4.7.5. Other Connectors
4.7.5. Other Connectors x
4.7.5.1. ADM/F Connectors 4.7.5.2. DP and HDMI Connectors 4.7.5.3. FMC+ Connectors
5. MBGA PCB Routing Guidelines x
5.1. Typical Design Rules for Type-IV HDI in a 0.5 mm MBGA 5.2. HSSI Breakout 5.3. EMIF Breakout
6. EMIF PCB Routing Guidelines (VPBGA and MBGA) x
6.1. General DDR Signal Routing Guideline on PCB 6.2. General Notes for EMIF Routing Guidelines Table 6.3. LPDDR5 Interface Design Guidelines 6.4. LPDDR4 Interface Design Guidelines 6.5. DDR4 Interface Design Guidelines 6.6. LPDDR5, LPDDR4, and DDR4 Simulation Strategy
6.1. General DDR Signal Routing Guideline on PCB x
6.1.1. FPGA DDR Break Out Routing 6.1.2. DRAM Break Out in Layout Routing 6.1.3. Ground Plane and Return Path
6.3. LPDDR5 Interface Design Guidelines x
6.3.1. LPDDR5 Memory Down Topology (Single Rank or Dual-Rank)
6.4. LPDDR4 Interface Design Guidelines x
6.4.1. LPDDR4 Memory Down Topology (Up to 32-bits Interface) 6.4.2. Tables for Comprehensive Routing Guidelines for Each LPDDR4 Signal
6.5. DDR4 Interface Design Guidelines x
6.5.1. Single Rank ×8 Memory Down Topology 6.5.2. Single Rank ×16 Memory Down Topology 6.5.3. VREF_CA/RESET Signal Routing Guidelines for Memory Down Topologies 6.5.4. Skew Matching Guidelines for DDR4 Memory Down Configurations 6.5.5. Power Delivery Recommendation for DDR4 Discrete Configurations
9. Power Distribution Network Design Guidelines x
9.1. Agilex™ 5 Power Distribution Network Design Guidelines Overview 9.2. Power Delivery Overview 9.3. Board Power Delivery Network Recommendations 9.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails 9.5. PCB PDN Design Guideline for Unused GTS Transceiver 9.6. PCB Voltage Regulator Recommendation for PCB Power Rails 9.7. Board PDN Simulations 9.8. Agilex™ 5 Device Family PDN Design Summary
9.1. Agilex™ 5 Power Distribution Network Design Guidelines Overview x
9.1.1. Device Guidelines Status for Agilex™ 5 Devices
9.2. Power Delivery Overview x
9.2.1. Power Architecture 9.2.2. Rail Merger Requirements 9.2.3. Power Rails Specification 9.2.4. Decoupling Capacitors Recommendation
9.2.1. Power Architecture x
9.2.1.1. Power Budget 9.2.1.2. Power Tree
9.2.1.2. Power Tree x
9.2.1.2.1. Recommended Power Tree for SmartVID Devices with GTS Transceiver 9.2.1.2.2. Recommended Power Tree for Non-SmartVID Devices with GTS Transceiver
9.2.3. Power Rails Specification x
9.2.3.1. Power Nets 9.2.3.2. Power Rails Tolerance 9.2.3.3. Power Nets and Transient Specifications
9.2.3.1. Power Nets x
9.2.3.1.1. Agilex™ 5 Package Power Nets and Subsystems Details
9.2.4. Decoupling Capacitors Recommendation x
9.2.4.1. Agilex™ 5 FPGA Packages Board-Level Decoupling Capacitors Summary 9.2.4.2. Agilex™ 5 GTS Transceiver Board-Level Decoupling Capacitors Summary
9.3. Board Power Delivery Network Recommendations x
9.3.1. Board Decoupling Capacitors Guide 9.3.2. FPGA Core Fabric VCC Voltage Regulator Selection 9.3.3. Remote Sense Connections 9.3.4. Load Line Requirements 9.3.5. VCC Core Board Current Slew Rate
9.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails x
9.4.1. GTS Transceiver Rail Board Connection and LC Filter Recommendation Under Noisy Voltage Regulator
9.5. PCB PDN Design Guideline for Unused GTS Transceiver x
9.5.1. PDN Design Guideline for Unused GTS Transceiver
1. Overview
2. BGA Footprint and Land Pattern
3. General PCB Design Considerations
4. VPBGA PCB Routing Guidelines
5. MBGA PCB Routing Guidelines
6. EMIF PCB Routing Guidelines (VPBGA and MBGA)
7. MIPI Interface Layout Design Guidelines (VPBGA and MBGA)
8. True Differential I/O Interface PCB Routing Guidelines (VPBGA and MBGA)
9. Power Distribution Network Design Guidelines
10. Document Revision History for the PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs

9.2.4.1. Agilex™ 5 FPGA Packages Board-Level Decoupling Capacitors Summary

Fabric or core decoupling capacitors are highly dependent on the size of the core or fabric (LE and number of GPIO pins) in the package.

Table 26.   Agilex™ 5 device FPGA Decoupling Capacitors SummaryThis table shows the PCB recommended FPGA decoupling capacitor requirement for the Agilex™ 5 device packages. This table does not include recommended decoupling/bulk capacitors at voltage regulators.
Device Agilex™ 5 Power and Thermal Calculator (PTC) Rail Name Bottom Side Capacitor FPGA Periphery Capacitor Note

FPGA A5E007B

B15A/B23B/B18A/B23A Fabric

 Merged VCC and VCCP 2x 4.7 uF 0402 — VR vendors capacitors recommendation must be compiled.

FPGA A5E013B

B23A/B32A/M16A/B23B/B18A Fabric

 Merged VCC and VCCP 4x 10 uF 0402 — VR vendors capacitors recommendation must be compiled.

FPGA A5E028B

B23A/B32A/M16A/B23B Fabric

 Merged VCC and VCCP 4x 10 uF 0402 — VR vendors capacitors recommendation must be compiled.

FPGA A5E065B

B23A/B32A Fabric

 Merged VCC and VCCP 4x 10 uF 0402 2x 47 uF 0805 VR vendors capacitors recommendation must be compiled. Use 47uF 0805 periphery capacitors on top-layer near FPGA.

FPGA A5E028A

B23A/B32A/M16A/B23B Fabric

 Merged VCC and VCCP 6x 10 uF 0402 — VR vendors capacitors recommendation must be compiled.

FPGA A5E065A

B23A/B32A Fabric

 Merged VCC and VCCP 6x 10 uF 0402 6x 47 uF 0805 VR vendors capacitors recommendation must be compiled. Use 47uF 0805 periphery capacitors on top-layer near FPGA.

FPGA A5D031

B23D/B32B Fabric

 Merged VCC and VCCP 6x 10 uF 0402 4x 47 uF 0805 VR vendors capacitors recommendation must be compiled. Use 47uF 0805 periphery capacitors on top-layer near FPGA.

FPGA A5D064

B32B Fabric

 Merged VCC and VCCP 8x 10uF 0402 8x 47 uF 0805 VR vendors capacitors recommendation must be compiled. Use 47uF 0805 periphery capacitors on top-layer near FPGA.
FPGA/HPS VCCL_HPS 2x 10 uF 0402 or 3x 4.7 uF 0201 1x 22 uF 0603 —
FPGA/HPS VCCL_HPS_CORE 1x 1 uF 0201 — Per HPS_CORE, CORE0_CORE1, CORE2, and CORE3.
FPGA/HPS

VCCPLL1_HPS

VCCPLL2_HPS

 1x 1 uF 0201 LC filter capacitors —
FPGA/HPS VCCIO_HPS 1x 1 uF 0201 — —
FPGA/HPS

VCCPLLDIG1_HPS

VCCPLLDIG2_HPS

 1x 1 uF 0201 LC filter capacitors —
FPGA VCCPT 2x 4.7 uF 0201 1x 10 uF 0402 —
FPGA VCCRCORE 1x 1 uF 0201 1x 10 uF 0402 —
FPGA/PIO VCCIO_PIO 2x 4.7 uF 0201 1x 10 uF 0402 Per I/O bank
FPGA/SDM VCCH_SDM 1x 1 uF 0201 — —
FPGA/SDM VCCL_SDM 2x 1 uF 0201 — —
FPGA/SDM VCC_IO_SDM 1x 1 uF 0201 — —
FPGA/SDM VCCL_ADC_SDM 1x 1 uF 0201 — —
FPGA/SDM VCCPLLDIG_SDM 1x 1 uF 0201 LC filter capacitors —
FPGA/SDM VCCIO_PIO_SDM 1x 1 uF 0201 — —
FPGA/SDM VCCADC 1x 1 uF 0201 LC filter capacitors —
FPGA/SDM VCCPLL_SDM 1x 1 uF 0201 LC filter capacitors —
FPGA/SDM VCCIO_SDM 1x 1 uF 0201 1x 10 uF 0402 —
FPGA/SDM VCCFUSEWR_SDM 1x 1 uF 0201 1x 4.7 uF 0402 —
FPGA/HVIO VCCPT_HVIO 2x 1 uF 0201 — Per I/O bank
FPGA/HVIO VCCIO_HVIO 1x 1 uF 0201 — Per I/O bank
Level Two Title