PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs
ID
821801
Date
8/29/2025
Public
1. Overview
2. BGA Footprint and Land Pattern
3. General PCB Design Considerations
4. VPBGA PCB Routing Guidelines
5. MBGA PCB Routing Guidelines
6. EMIF PCB Routing Guidelines (VPBGA and MBGA)
7. MIPI Interface Layout Design Guidelines (VPBGA and MBGA)
8. True Differential I/O Interface PCB Routing Guidelines (VPBGA and MBGA)
9. Power Distribution Network Design Guidelines
10. Document Revision History for the PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs
9.1. Agilex™ 5 Power Distribution Network Design Guidelines Overview
9.2. Power Delivery Overview
9.3. Board Power Delivery Network Recommendations
9.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails
9.5. PCB PDN Design Guideline for Unused GTS Transceiver
9.6. PCB Voltage Regulator Recommendation for PCB Power Rails
9.7. Board PDN Simulations
9.8. Agilex™ 5 Device Family PDN Design Summary
6.2. General Notes for EMIF Routing Guidelines Table
The following general notes apply to the EMIF routing guidelines tables in subsequent topics:
- All spacing requirements are the minimum requirement to be met on PCB in EMIF routing guidelines table.
- In the routing guideline table, h represents the trace-to-nearest-reference-plane height or distance. Board designer should use the formula in the routing guide table to calculate the correct spacing requirements.
- There is no differential impedance target for CLK and DQS. As a board designer, you should follow the EMIF routing table and keep traces closely coupled.
- The trace length and spacing in the guideline table are based on FR-4 level PCB material and the PCB layout routing with the worst-case crosstalk. You can perform simulation if you do not follow the requirements in the routing guide table.
- SL stands for stripline routing recommendation and US stands for upper surface (microstrip) routing recommendation in guideline tables.
- You must design trace widths of BO, BO1, BO2, and BI based on the actual PCB stack-up and PCB design. It would be better if trace widths of BO, BO1, BO2, and BI can be designed closer to target impedance of the M segment.
- Include the FPGA package per-pin skew and PCB delay for skew matching.
- Does not require length matching on the Alert signal and Reset signal.
- Altera recommends that you perform skew matching in time (picosecond).
- The minimum trace widths specified in the BO and BI sections of the guideline are 3 mil for MBGA (stripline and microstrip) and VPBGA (stripline), and 4 mil for VPBGA (microstrip). Altera recommends using wider spacing in the PCB layout when feasible.