PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs

ID 821801
Date 8/29/2025
Public
Document Table of Contents

6.3. LPDDR5 Interface Design Guidelines

Agilex™ 5 E-Series Group B devices support LPDDR5 interfaces for memory down configuration only. Both thin and thick PCB stack-ups are supported.