PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs

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ID 821801
Date 8/29/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. BGA Footprint and Land Pattern 3. General PCB Design Considerations 4. VPBGA PCB Routing Guidelines 5. MBGA PCB Routing Guidelines 6. EMIF PCB Routing Guidelines (VPBGA and MBGA) 7. MIPI Interface Layout Design Guidelines (VPBGA and MBGA) 8. True Differential I/O Interface PCB Routing Guidelines (VPBGA and MBGA) 9. Power Distribution Network Design Guidelines 10. Document Revision History for the PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs
1. Overview x
1.1. Agilex™ 5 FPGAs and SoCs Packages
2. BGA Footprint and Land Pattern x
2.1. Metal-Defined Board Pad 2.2. Spoked Pad 2.3. Wide Trace Metal-Defined Pad 2.4. Solder Mask-Defined Pad 2.5. Recommended Land Patterns
3. General PCB Design Considerations x
3.1. Impedance Tolerances 3.2. Reference Planes 3.3. Layer Assignment 3.4. Via Drill Size 3.5. Fiber Weave 3.6. PCB Traces 3.7. PCB Vias 3.8. AC Coupling Capacitors 3.9. Other Considerations
3.6. PCB Traces x
3.6.1. Zig-Zag Routing 3.6.2. Image Rotation
4. VPBGA PCB Routing Guidelines x
4.1. Pin Distribution and Ball Pitches 4.2. Fan-Out and Routing Strategy 4.3. Power Pins 4.4. HSSI Reference PCB Stack-up 4.5. Agilex™ 5 GTS Transceiver 4.6. GTS Transceiver PCIe* 4.0 16 GT/s NRZ Interface Design Guidelines 4.7. GTS Transceiver Ethernet 25G NRZ Interface Design Guidelines
4.5. Agilex™ 5 GTS Transceiver x
4.5.1. HSSI Pin-Field Breakout for VPBGA
4.6. GTS Transceiver PCIe* 4.0 16 GT/s NRZ Interface Design Guidelines x
4.6.1. GTS Transceiver Channel Recommendations 4.6.2. General Guidelines for GTS Transceiver PCIe* Gen 4.0 Interface 4.6.3. PCIe* Add-In Card Edge Finger
4.7. GTS Transceiver Ethernet 25G NRZ Interface Design Guidelines x
4.7.1. GTS Transceiver Channel Recommendations 4.7.2. General Guidelines for GTS Transceiver Ethernet Interface 4.7.3. Quad Small Form-factor Pluggable Connector Routing 4.7.4. Small Form-factor Pluggable (SFP) Connector Routing 4.7.5. Other Connectors
4.7.5. Other Connectors x
4.7.5.1. ADM/F Connectors 4.7.5.2. DP and HDMI Connectors 4.7.5.3. FMC+ Connectors
5. MBGA PCB Routing Guidelines x
5.1. Typical Design Rules for Type-IV HDI in a 0.5 mm MBGA 5.2. HSSI Breakout 5.3. EMIF Breakout
6. EMIF PCB Routing Guidelines (VPBGA and MBGA) x
6.1. General DDR Signal Routing Guideline on PCB 6.2. General Notes for EMIF Routing Guidelines Table 6.3. LPDDR5 Interface Design Guidelines 6.4. LPDDR4 Interface Design Guidelines 6.5. DDR4 Interface Design Guidelines 6.6. LPDDR5, LPDDR4, and DDR4 Simulation Strategy
6.1. General DDR Signal Routing Guideline on PCB x
6.1.1. FPGA DDR Break Out Routing 6.1.2. DRAM Break Out in Layout Routing 6.1.3. Ground Plane and Return Path
6.3. LPDDR5 Interface Design Guidelines x
6.3.1. LPDDR5 Memory Down Topology (Single Rank or Dual-Rank)
6.4. LPDDR4 Interface Design Guidelines x
6.4.1. LPDDR4 Memory Down Topology (Up to 32-bits Interface) 6.4.2. Tables for Comprehensive Routing Guidelines for Each LPDDR4 Signal
6.5. DDR4 Interface Design Guidelines x
6.5.1. Single Rank ×8 Memory Down Topology 6.5.2. Single Rank ×16 Memory Down Topology 6.5.3. VREF_CA/RESET Signal Routing Guidelines for Memory Down Topologies 6.5.4. Skew Matching Guidelines for DDR4 Memory Down Configurations 6.5.5. Power Delivery Recommendation for DDR4 Discrete Configurations
9. Power Distribution Network Design Guidelines x
9.1. Agilex™ 5 Power Distribution Network Design Guidelines Overview 9.2. Power Delivery Overview 9.3. Board Power Delivery Network Recommendations 9.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails 9.5. PCB PDN Design Guideline for Unused GTS Transceiver 9.6. PCB Voltage Regulator Recommendation for PCB Power Rails 9.7. Board PDN Simulations 9.8. Agilex™ 5 Device Family PDN Design Summary
9.1. Agilex™ 5 Power Distribution Network Design Guidelines Overview x
9.1.1. Device Guidelines Status for Agilex™ 5 Devices
9.2. Power Delivery Overview x
9.2.1. Power Architecture 9.2.2. Rail Merger Requirements 9.2.3. Power Rails Specification 9.2.4. Decoupling Capacitors Recommendation
9.2.1. Power Architecture x
9.2.1.1. Power Budget 9.2.1.2. Power Tree
9.2.1.2. Power Tree x
9.2.1.2.1. Recommended Power Tree for SmartVID Devices with GTS Transceiver 9.2.1.2.2. Recommended Power Tree for Non-SmartVID Devices with GTS Transceiver
9.2.3. Power Rails Specification x
9.2.3.1. Power Nets 9.2.3.2. Power Rails Tolerance 9.2.3.3. Power Nets and Transient Specifications
9.2.3.1. Power Nets x
9.2.3.1.1. Agilex™ 5 Package Power Nets and Subsystems Details
9.2.4. Decoupling Capacitors Recommendation x
9.2.4.1. Agilex™ 5 FPGA Packages Board-Level Decoupling Capacitors Summary 9.2.4.2. Agilex™ 5 GTS Transceiver Board-Level Decoupling Capacitors Summary
9.3. Board Power Delivery Network Recommendations x
9.3.1. Board Decoupling Capacitors Guide 9.3.2. FPGA Core Fabric VCC Voltage Regulator Selection 9.3.3. Remote Sense Connections 9.3.4. Load Line Requirements 9.3.5. VCC Core Board Current Slew Rate
9.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails x
9.4.1. GTS Transceiver Rail Board Connection and LC Filter Recommendation Under Noisy Voltage Regulator
9.5. PCB PDN Design Guideline for Unused GTS Transceiver x
9.5.1. PDN Design Guideline for Unused GTS Transceiver
1. Overview
2. BGA Footprint and Land Pattern
3. General PCB Design Considerations
4. VPBGA PCB Routing Guidelines
5. MBGA PCB Routing Guidelines
6. EMIF PCB Routing Guidelines (VPBGA and MBGA)
7. MIPI Interface Layout Design Guidelines (VPBGA and MBGA)
8. True Differential I/O Interface PCB Routing Guidelines (VPBGA and MBGA)
9. Power Distribution Network Design Guidelines
10. Document Revision History for the PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs

9.7. Board PDN Simulations

This section describes the post-layout simulation of the PDN and Transient Noise Analysis as shown in the following figure. This methodology is applicable to Agilex™ 5 device family board designs and system-level simulations.

Figure 85.  Methodology for Device PDN and Transient Noise Analysis Step load at the package pin is injected to the PCB model to meet voltage droop (DC + AC) at the package pin.

Altera recommends that you follow the preceding guidelines to design all power rails on the PCB with the recommended decoupling capacitors, voltage regulators, and LC filtering. In the post-layout phase, perform the IR drop and transient (time domain) PDN analysis for the PCB only. This means, unconventionally, Altera do not recommend impedance target and frequency target analysis (frequency domain simulation) for the Agilex™ 5 device.

To ensure the PDN design performance is within the required tolerance or specification in the Power Rails Tolerance section, Altera recommends performing time domain post-layout PDN simulation for some critical power nets such as VCC core, VCCP, VCCPT, VCCIO_PIO, VCC_HSSI, and power rails for GTS transceiver.

PDN time domain simulation is only performed on PCB from voltage regulator to package ball. Therefore, package, OPDs, and on-chip models are not required for the PDN time domain simulation.

The following steps show the process of time domain PDN (as shown in the Time Domain PDN Test Bench Example for Agilex™ 5 A5E065B VCC+VCCP figure):

  1. Obtain the implemented VRM SPICE model for the target power rail.
  2. Extract post-layout PCB model (HSPICE or scattering parameters) of the PCB with integrated decoupling capacitors and LC filtering from the voltage regulator.
    1. Use tools such as PowerSI to extract the required scattering parameters model, including the VRM recommended bulk decoupling capacitors provided by vendor. Ensure that the extracted PCB scattering parameter model covers the frequency range from DC up to 2 GHz.
    2. Convert the scattering parameters to a circuit model using any broadband SPICE or IDEM tool to avoid potential issues.
    3. To prevent simulation divergence, you can include small to medium decoupling capacitors and separately define ports for large and bulk capacitors in the PCB extraction process. Then you can add the large and bulk capacitors SPICE models externally in the schematic.
  3. Build a schematic in any possible EDA tool (such as Keysight ADS, Cadence, LTspice, or Simplis) with the voltage regulator model (possible HSPICE model) and PCB model extracted from previous step.
    • This schematic represents the voltage regulator plus the PCB or decoupling capacitors model up to the package pins.
    • Package, OPDs, or die model is not built into this schematic (step load at package pin covers frequencies for only PCB, which means high frequency current components are eliminated through package and on-die).
    • Connect the sense pins from the package pin feedback to the voltage regulator sense pins.
  4. Connect the maximum step load current at the package pins shown in the Power Nets and Transient Specifications section (for example, for Agilex™ 5 A5E065B VCC+VCCP has a 74 A/µs slew rate and step load of 3.7 A ).
  5. Probe voltage drop at the package pin to see if the power rail specification in the Power Rails Tolerance section is met (for example, for VCC+VCCP, the DC+AC voltage tolerance is ±3%).
    • If it is not meeting the package power rail tolerance or specification in the Power Rails Tolerance section, you must check the PCB and adjust the number of decoupling capacitors or their locations.
Figure 86.  Time Domain PDN Test Bench Example for Agilex™ 5 A5E065B VCC+VCCP "A" is the VCC node at the package ball (all VCC pins at the package are connected to A). The offset of Voltage at "A" must be within the voltage tolerance.

The preceding figure shows a simplified schematic for the PDN transient simulation. To avoid non-convergence condition in Time-Domain simulation, Altera recommends that you include only small decoupling capacitors in the PCB model extraction and define ports for large/bulk decoupling capacitors at PCB level and add them to the schematic as shown in the Time Domain PDN Test Bench Example for Agilex™ 5 A5E065B VCC+VCCP figure manually.

Some of the PCB power rails in the recommended power tree in the Power Tree section is built by merging various power rails (with or without filter). Define ports in the PCB modeling for each power rail so you can inject the step load for that power rail in the PDN simulation schematic.

The recommended step load and the static current (obtained from PTC) in a format of a pulse for each power rail is added to power rail ports in the PDN simulation schematic (e.g., Time Domain PDN Test Bench Example for Agilex™ 5 A5E065B VCC+VCCP figure) and the voltage droop and overshoot are measured against the specification listed in the Power Rails Tolerance section.

The PDN IR drop analysis is a DC simulation and must be performed on all power rails on the PCB up to package pins to meet the electrical specifications listed in the Agilex™ 5 FPGAs and SoCs Device Data Sheet.

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