PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs

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ID 821801
Date 8/29/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. BGA Footprint and Land Pattern 3. General PCB Design Considerations 4. VPBGA PCB Routing Guidelines 5. MBGA PCB Routing Guidelines 6. EMIF PCB Routing Guidelines (VPBGA and MBGA) 7. MIPI Interface Layout Design Guidelines (VPBGA and MBGA) 8. True Differential I/O Interface PCB Routing Guidelines (VPBGA and MBGA) 9. Power Distribution Network Design Guidelines 10. Document Revision History for the PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs
1. Overview x
1.1. Agilex™ 5 FPGAs and SoCs Packages
2. BGA Footprint and Land Pattern x
2.1. Metal-Defined Board Pad 2.2. Spoked Pad 2.3. Wide Trace Metal-Defined Pad 2.4. Solder Mask-Defined Pad 2.5. Recommended Land Patterns
3. General PCB Design Considerations x
3.1. Impedance Tolerances 3.2. Reference Planes 3.3. Layer Assignment 3.4. Via Drill Size 3.5. Fiber Weave 3.6. PCB Traces 3.7. PCB Vias 3.8. AC Coupling Capacitors 3.9. Other Considerations
3.6. PCB Traces x
3.6.1. Zig-Zag Routing 3.6.2. Image Rotation
4. VPBGA PCB Routing Guidelines x
4.1. Pin Distribution and Ball Pitches 4.2. Fan-Out and Routing Strategy 4.3. Power Pins 4.4. HSSI Reference PCB Stack-up 4.5. Agilex™ 5 GTS Transceiver 4.6. GTS Transceiver PCIe* 4.0 16 GT/s NRZ Interface Design Guidelines 4.7. GTS Transceiver Ethernet 25G NRZ Interface Design Guidelines
4.5. Agilex™ 5 GTS Transceiver x
4.5.1. HSSI Pin-Field Breakout for VPBGA
4.6. GTS Transceiver PCIe* 4.0 16 GT/s NRZ Interface Design Guidelines x
4.6.1. GTS Transceiver Channel Recommendations 4.6.2. General Guidelines for GTS Transceiver PCIe* Gen 4.0 Interface 4.6.3. PCIe* Add-In Card Edge Finger
4.7. GTS Transceiver Ethernet 25G NRZ Interface Design Guidelines x
4.7.1. GTS Transceiver Channel Recommendations 4.7.2. General Guidelines for GTS Transceiver Ethernet Interface 4.7.3. Quad Small Form-factor Pluggable Connector Routing 4.7.4. Small Form-factor Pluggable (SFP) Connector Routing 4.7.5. Other Connectors
4.7.5. Other Connectors x
4.7.5.1. ADM/F Connectors 4.7.5.2. DP and HDMI Connectors 4.7.5.3. FMC+ Connectors
5. MBGA PCB Routing Guidelines x
5.1. Typical Design Rules for Type-IV HDI in a 0.5 mm MBGA 5.2. HSSI Breakout 5.3. EMIF Breakout
6. EMIF PCB Routing Guidelines (VPBGA and MBGA) x
6.1. General DDR Signal Routing Guideline on PCB 6.2. General Notes for EMIF Routing Guidelines Table 6.3. LPDDR5 Interface Design Guidelines 6.4. LPDDR4 Interface Design Guidelines 6.5. DDR4 Interface Design Guidelines 6.6. LPDDR5, LPDDR4, and DDR4 Simulation Strategy
6.1. General DDR Signal Routing Guideline on PCB x
6.1.1. FPGA DDR Break Out Routing 6.1.2. DRAM Break Out in Layout Routing 6.1.3. Ground Plane and Return Path
6.3. LPDDR5 Interface Design Guidelines x
6.3.1. LPDDR5 Memory Down Topology (Single Rank or Dual-Rank)
6.4. LPDDR4 Interface Design Guidelines x
6.4.1. LPDDR4 Memory Down Topology (Up to 32-bits Interface) 6.4.2. Tables for Comprehensive Routing Guidelines for Each LPDDR4 Signal
6.5. DDR4 Interface Design Guidelines x
6.5.1. Single Rank ×8 Memory Down Topology 6.5.2. Single Rank ×16 Memory Down Topology 6.5.3. VREF_CA/RESET Signal Routing Guidelines for Memory Down Topologies 6.5.4. Skew Matching Guidelines for DDR4 Memory Down Configurations 6.5.5. Power Delivery Recommendation for DDR4 Discrete Configurations
9. Power Distribution Network Design Guidelines x
9.1. Agilex™ 5 Power Distribution Network Design Guidelines Overview 9.2. Power Delivery Overview 9.3. Board Power Delivery Network Recommendations 9.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails 9.5. PCB PDN Design Guideline for Unused GTS Transceiver 9.6. PCB Voltage Regulator Recommendation for PCB Power Rails 9.7. Board PDN Simulations 9.8. Agilex™ 5 Device Family PDN Design Summary
9.1. Agilex™ 5 Power Distribution Network Design Guidelines Overview x
9.1.1. Device Guidelines Status for Agilex™ 5 Devices
9.2. Power Delivery Overview x
9.2.1. Power Architecture 9.2.2. Rail Merger Requirements 9.2.3. Power Rails Specification 9.2.4. Decoupling Capacitors Recommendation
9.2.1. Power Architecture x
9.2.1.1. Power Budget 9.2.1.2. Power Tree
9.2.1.2. Power Tree x
9.2.1.2.1. Recommended Power Tree for SmartVID Devices with GTS Transceiver 9.2.1.2.2. Recommended Power Tree for Non-SmartVID Devices with GTS Transceiver
9.2.3. Power Rails Specification x
9.2.3.1. Power Nets 9.2.3.2. Power Rails Tolerance 9.2.3.3. Power Nets and Transient Specifications
9.2.3.1. Power Nets x
9.2.3.1.1. Agilex™ 5 Package Power Nets and Subsystems Details
9.2.4. Decoupling Capacitors Recommendation x
9.2.4.1. Agilex™ 5 FPGA Packages Board-Level Decoupling Capacitors Summary 9.2.4.2. Agilex™ 5 GTS Transceiver Board-Level Decoupling Capacitors Summary
9.3. Board Power Delivery Network Recommendations x
9.3.1. Board Decoupling Capacitors Guide 9.3.2. FPGA Core Fabric VCC Voltage Regulator Selection 9.3.3. Remote Sense Connections 9.3.4. Load Line Requirements 9.3.5. VCC Core Board Current Slew Rate
9.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails x
9.4.1. GTS Transceiver Rail Board Connection and LC Filter Recommendation Under Noisy Voltage Regulator
9.5. PCB PDN Design Guideline for Unused GTS Transceiver x
9.5.1. PDN Design Guideline for Unused GTS Transceiver
1. Overview
2. BGA Footprint and Land Pattern
3. General PCB Design Considerations
4. VPBGA PCB Routing Guidelines
5. MBGA PCB Routing Guidelines
6. EMIF PCB Routing Guidelines (VPBGA and MBGA)
7. MIPI Interface Layout Design Guidelines (VPBGA and MBGA)
8. True Differential I/O Interface PCB Routing Guidelines (VPBGA and MBGA)
9. Power Distribution Network Design Guidelines
10. Document Revision History for the PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs

6.4.2. Tables for Comprehensive Routing Guidelines for Each LPDDR4 Signal

The following tables provide comprehensive routing guidelines for each of the LPDDR4 signals based on memory down topology, such as the trace impedance, the total trace length, and the maximum main segment trace length. You can derive the maximum main segment trace length by subtracting the break-out segment and break-in segment trace length from the total trace length.
Table 8.  Stripline Routing Guide for LPDDR4 Memory Down TopologyIn this table, h represents the trace-to-nearest-reference-plane height or distance. SL stands for stripline routing recommendation and US stands for upper surface (microstrip) routing recommendation.
Signal Group Segment Routing Layer Maximum Length (mil) Target Zse (Ω) Trace Spacing S1 (mil): Within Group Trace Spacing S2 (mil): CMD/CTRL/CLK to DQ/DQS Trace Spacing S3 (mil): DQ Nibble to Nibble Trace Spacing (mil), Within DIFF pair Trace Spacing (mil), DQS pair to DQ Trace Spacing (mil), CLK pair to CMD/CTRL/CKE
Segment Total MB
CA/CS/CKE/CLK (Direct Connect) BO1/BO2 SL 450 4000   3 3h   4   3h
M SL   40 2h 3h   4   3h
BI SL 50   2h 3h   4   3h
CA/CS/CKE/CLK (Daisy) BO SL 500 4000   3 3h   4   3h
M SL   40 2h 3h   4   3h
BI SL 1000   2h 3h   4   3h
CA/CS/CKE/CLK (T) BO SL 500 4000   3 3h   4   3h
M SL 2500 40 2h 3h   4   3h
BI SL 1000 50+ 2h 3h   4   3h
DQ BO1 US 50 4000   3   3h      
BO2 SL 1000   3   3h      
M SL   40 2h   3h      
BI US 50   2h   3h      
DQS BO1 US 50 4000         4 3  
BO2 SL 1000         4 3  
M SL   40       4 3h  
BI US 50         4 3h  
Table 9.  Microstrip Routing Guide for LPDDR4 Memory Down TopologyIn this table, h represents the trace-to-nearest-reference-plane height or distance. SL stands for stripline routing recommendation and US stands for upper surface (microstrip) routing recommendation.
Signal Group Segment Routing Layer Maximum Length (mil) Target Zse (Ω) Trace Spacing S1 (mil): Within Group Trace Spacing S3 (mil): DQ Nibble to Nibble Trace Spacing (mil), Within DIFF pair Trace Spacing (mil), DQS pair to DQ
Segment Total MB
DQ BO US 100 3000  

MBGA package: 3

VPBGA package: 4

      
M US   45 3h 3h    
BI US 300   4      
DQS BO US 100 3000      

MBGA package: 3

VPBGA package: 4

MBGA package: 3

VPBGA package: 4
M US   45     4 4h
BI US 300       4 3

Reset signal routing design also follows the CMD/ADD/CTRL routing design. Keep the space at least 3×H (dielectric height) between the Reset signal to other signals on the same layer (measured edge to edge).

Skew matching for LPDDR4 interfaces consists of both package routing skew and PCB physical routing skew. Use three times of dielectric height for serpentine routing spacing. Skew matching of CA and CTRL with respect to the clock signals to ensure signals at the receiver are correctly sampled. In addition, there are skew matching requirement for DQ and DQS within a byte group, DQS, and CLK.

Table 10.  Skew Matching Requirement for LPDDR4 Memory Down TopologyThis table provides a detailed skew matching guideline.
Length Matching Rules Time
Length matching between CLK and DQS per x16 -340 ps < CLK - DQS < 170 ps
Length matching between DQ and DQS per x8 -68 ps < DQ - DQS < 43 ps
Length matching between DQ signals per x8 < 43 ps
Length matching between CLK and CA bits per x16 -34 ps < CLK - CA < 34 ps
Length matching between CA bits per x16 < 34 ps
Length matching between CLK and CS/CKE per x16 -85 ps < CKL - CS/CKE < 85 ps
Length matching between CS/CKE bits per x16 < 34 ps
Length matching between DQS_N and DQS_P < 1 ps
Length matching between CLK_N and CLK_P < 1 ps
Include package length in length matching Required
Length matching for CA/CS/CKE/CLK Tee segments (BI) < 1 ps

LPDDR4 eye margin is sensitive to crosstalk, especially when the signals are routed on deep layers. Note the deep-layer vertical transition induces more vertical coupling and crosstalk between signals. You can conduct simulations to determine the routing layer and evaluate the necessity of backdrilling.

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