PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs

ID 821801
Date 8/29/2025
Public
Document Table of Contents

6.4.1. LPDDR4 Memory Down Topology (Up to 32-bits Interface)

LPDDR4 memory down supports single rank and dual-rank configurations up to 32 bits. There are four DRAM interface signal groupings—data group, command-address group, control group, and clock group. The connection between the FPGA and DRAM device uses point-to-point topology as shown in the following figures.
Figure 61. Stripline Routing for Data, CA, CTRL, and Clock Signals Point-to-Point TopologyThis figure shows the stripline routing for inner pins.


Figure 62. Stripline Routing for Reset SignalsThis figure shows the Reset signal routing topology. Altera recommends using 1.0 KΩ pull-down resistor for Reset signal termination


Figure 63. Microstrip Routing on the Outer Layer for Data Signals Point-to-Point TopologyThis figure shows the microstrip routing for the edge pins of BGA per byte.


Figure 64. Stripline Routing for CA, CLK, and CTRL Daisy-Chain and T-Line TopologyThis figure shows the daisy-chain and T-Line connections topology for CA, CLK, and CTRL signals for LPDDR4.