PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs
4.6.2. General Guidelines for GTS Transceiver PCIe* Gen 4.0 Interface
- Intra pair skew: ±1mil
BGA Breakout Optimization
Through hole vias with backdrill are used. As outlined in the General Design Considerations section, note the change of impedance control tolerance, total insertion loss, crosstalk and so forth for microstrip routing especially when implementing long microstrip length. Altera recommends 3D field solver simulation for BGA breakout optimization. Try to make return loss lower than -15 dB at Nyquist frequency (lower than -20 dB is better) and control the impedance changing of cut-out area as small as possible (better within ±5 Ω).
Simulation results for 18 mil pad size have been also presented. Both pad sizes can get good performance.
The impedance is lower due to the large capacitance caused by larger pad size of 18 mil. While the return loss is 3 to 4 dB higher, it meets the -15 dB requirement. A larger anti-pad size such as 30 mil improves return loss performance as shown in the Simulation Results of L3 Breakout Using 18 mil Pad Size figure.