PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs
9.2.3.2. Power Rails Tolerance
This section describes the power rails tolerance and budget (AC tolerance + VR accuracy) on board at package level for the Agilex™ 5 device family. The rail tolerance must be met at the FPGA package ball. Consider the following instructions to measure the rail tolerance:
- VCCL (core power net) measurement is taken at the FPGA remote differential sense lines (there are assigned differential sense pins at FPGA package) with the scope set to bandwidth limited at 20 MHz.
- For other power rails except VCCL, the rail tolerance must be met at the board vias on the bottom layer directly connected to the package power balls.
- For all other power rails with the objective to compensate the IR drop on those specific power rails, place their respective voltage regulator sense point within the FPGA pin field, connecting to one of the rail's BGA pins which represents the worst IR drop on the path.
| Power Tree Rail Name | Vnom (Required) (V) |
Recommended VR Accuracy (% of Vnom) |
Recommended VR Ripple (% of Vnom) |
Recommended AC Transient (% of Vnom) |
Maximum AC Tolerance + VR Accuracy6 (% of Vnom) |
|---|---|---|---|---|---|
| VCCL | SmartVID (0.8) | ±0.5% | ±2.5% | ±3% | |
| P0V8_GR1 | 0.8 | ±0.5% | ±2.5% | ±3% | |
| P1V0_GR1 | 1.0 | ±0.5% | ±2.0% | ±2.5% | |
P1V8_GR2a7 : VCCEHT_GTS |
1.8 | ±0.5% | ±2.0% | ±2.5% | |
P1V8_GR2a7: VCCPT_HVIO |
1.8 | ±0.5% | ±1%8 | ±1.5% | ±3% |
P1V8_GR2a7:
|
1.8 | ±0.5% | ±1%8 | ±3.5% | ±5% |
P1V2_GR2b9 :
|
1.2 | ±0.5% | ±1%8 | ±1.5% | ±3% |
P1V2_GR2b9: VCCRCORE |
1.2 | ±0.5% | ±1%8 | ±3.5% | ±5% |
| VCCIO_HVIO | 3.3/2.5/1.8 | ±0.5% | ±1%8 | ±1.5% | ±3% |
| Power Tree Rail Name | Vnom (Required) (V) |
Recommended VR Accuracy (% of Vnom) |
Recommended VR Ripple (% of Vnom) |
Recommended AC Transient (% of Vnom) |
Maximum AC Tolerance + VR Accuracy6 (% of Vnom) |
|---|---|---|---|---|---|
| VCCL | 0.8 (–4S) 0.78 (–5S) 0.75 (–6S, –6X) |
±0.5% | ±2.5% | ±3% | |
| P1V0_GR1 | 1.0 | ±0.5% | ±2.0% | ±2.5% | |
P1V8_GR2a7: VCCEHT_GTS |
1.8 | ±0.5% | ±2.0% | ±2.5% | |
P1V8_GR2a7: VCCPT_HVIO |
1.8 | ±0.5% | ±1%8 | ±1.5% | ±3% |
P1V8_GR2a7:
|
1.8 | ±0.5% | ±1%8 | ±3.5% | ±5% |
P1V2_GR2b9:
|
1.2 | ±0.5% | ±1%8 | ±1.5% | ±3% |
P1V2_GR2b9: VCCRCORE |
1.2 | ±0.5% | ±1%8 | ±3.5% | ±5% |
| VCCIO_HVIO | 3.3/2.5/1.8 | ±0.5% | ±1%8 | ±1.5% | ±3% |
The Agilex™ 5 FPGAs and SoCs Device Data Sheet details the specifications for each power rail at the package level. To reduce PCB costs, you can combine some power rails using a single voltage regulator to feed the power rails. The AC and DC specification in this design guideline reflects this approach, however this is optional.
Using a voltage regulator, you can merge the analog power rails on the PCB if their nominal voltages match. Ensure that the combined power rail specifications and voltage regulator meet the most stringent specifications of the package power rails.
The Agilex™ 5 SmartVID Device PCB Power Rail Tolerance and Agilex™ 5 Fixed Voltage Device PCB Power Rail Tolerance tables show the power rail tolerance (AC tolerance + VR accuracy) based on the power tree in the Power Tree section.
When you use a different power tree, ensure that the rail tolerance of each power net remains within the recommended grouping category in the Agilex™ 5 SmartVID Device PCB Power Rail Tolerance and Agilex™ 5 Fixed Voltage Device PCB Power Rail Tolerance tables.