PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs

ID 821801
Date 8/29/2025
Public
Document Table of Contents

6.5.1. Single Rank ×8 Memory Down Topology

Single Rank ×8 Memory Down Topology

The single rank ×8 discrete interface covers data bytes (DQ/DQS), address signals, command signals (BA, BG, RAS, CAS, WE, ACT, PAR), control signals (CKE, CS, ODT) and CLKs.

The following figure illustrate the single rank ×8 memory down topology stripline routing for the BGA inner pins design example.

Figure 65. Signals Connections for Supported Signals in Single Rank ×8 Discrete Topology
Figure 66. Microstrip Routing on the Outer Layer for DDR4 Single Rank ×8 Memory Down TopologyThis figure illustrates the single rank ×8 memory down topology for microstrip routing on the outer layer for BGA edge pins
Table 11.  Stripline Routing Guidelines for Single Rank Discrete Memory TopologyThis table shows the stripline routing for BGA inner pins and microstrip routing for BGA outer pins with the single rank ×8 memory down topology. In this table, h represents the trace-to-nearest-reference-plane height or distance. SL stands for stripline routing recommendation and US stands for upper surface (microstrip) routing recommendation.
Signal Group Segment Routing Layer Maximum Length (mil) Target Zse (Ω) Trace Spacing S1 (mil): Within Group Trace Spacing S2 (mil): CMD/CTRL/CLK to DQ/DQS Trace Spacing S3 (mil): DQ Nibble to Nibble Trace Spacing (mil), Within DIFF pair Trace Spacing (mil), DQS pair to DQ Trace Spacing (mil), CLK pair to CMD/CTRL/CKE Rtt/Ctt
Segment Total MB
CLK BO1 US 50 To first DRAM: 4000

To last DRAM: 9600

  3 3h   4   3h R1=36 Ω

C1=10 nF

BO2 SL 1000   3 3h   4   3h
M SL   40   3h   4   3h
BI1 US 50     3h   4   3h
BI2 SL 700 50+   3h   4   3h
T1 SL 300     3h   4   3h
T2 US 50     3h   4   3h
CMD/CTRL/Alert BO1 US 50 To first DRAM: 4000

To last DRAM: 9600

  3 3h         R1=36 Ω
BO2 SL 1000   3 3h        
M SL   40 2h 3h        
BI1 US 50   2h 3h        
BI2 SL 700 50+ 2h 3h        
T1 SL 300   2h 3h        
T2 US 50   2h 3h        
DQ BO1 US 50 5000   3   3h        
BO2 SL 1000   3   3h      
M SL   45 2h   3h      
BI US 50   2h   3h      
DQS BO1 US 50 5000         4 3  
BO2 SL 1000         4 3  
M SL   45       4 3h  
BI US 50         4 3h  
Table 12.  Microstrip Routing Guideline for Single Rank Discrete Memory TopologyIn this table, h represents the trace-to-nearest-reference-plane height or distance. SL stands for stripline routing recommendation and US stands for upper surface (microstrip) routing recommendation.
Signal Group Segment Routing Layer Maximum Length (mil) Target Zse (Ω) Trace Spacing S1 (mil): Within Group Trace Spacing S3 (mil), DQ Nibble to Nibble Trace Spacing (mil), Within DIFF pair Trace Spacing (mil), DQS pair to DQ
Segment Total MB
DQ BO US 100 3000  

MBGA package: 3

VPBGA package: 4

     
M US   45 3h 3h    
BI US 300   4      
DQS BO US 100 3000      

MBGA package: 3

VPBGA package: 4

MBGA package: 3

VPBGA package: 4

M US   45     4 4h
BI US 300       4 4