Intel® MAX® 10 High-Speed LVDS I/O User Guide

ID 683760
Date 11/01/2021
Public
Document Table of Contents

7.1. Soft LVDS Parameter Settings

There are four groups of options: General , PLL Settings , Receiver Settings , and Transmitter Settings
Table 11.   Soft LVDS Parameters - General
Parameter Condition Allowed Values Description
Power Supply Mode
  • Dual Supply
  • Single Supply
Specifies whether the target device is a single or dual supply device.
Functional mode
  • RX
  • TX
Specifies the functional mode for the Soft LVDS IP core:
  • RX—specifies the IP is an LVDS receiver.
  • TX—specifies the IP is an LVDS transmitter.
Number of channels 1–18

Specifies the number of LVDS channels.

SERDES factor 1, 2, 4, 5, 6, 7, 8, 9, 10

Specifies the number of bits per channel.

Table 12.   Soft LVDS Parameters - PLL Settings
Parameter Condition Allowed Values Description
Use external PLL Not applicable for x1 and x2 modes.
  • On
  • Off

Specifies whether the Soft LVDS IP core generates a PLL or connects to a user-specified PLL.

Data rate Refer to the device datasheet.

Specifies the data rate going out of the PLL. The multiplication value for the PLL is OUTPUT_DATA_RATE divided by INCLOCK_ PERIOD.

Inclock frequency Depends on Data rate.

Specifies the input clock frequency to the PLL in MHz.

Enable rx_locked port
  • General, Functional mode = RX
  • Use external PLL = Off
  • On
  • Off

If turned on, enables the rx_locked port.

Enable tx_locked port
  • General, Functional mode = TX
  • Use external PLL = Off
  • On
  • Off

If turned on, enables the tx_locked port.

Enable pll_areset port Use external PLL = Off
  • On
  • Off

If turned on, enables the pll_areset port in internal PLL mode.

In external PLL mode, the pll_areset port is not available.

Enable tx_data_reset port
  • General, Functional mode = TX
  • Use external PLL = On
  • On
  • Off

If turned on, enables the tx_data_reset port.

Enable rx_data_reset port
  • General, Functional mode = RX
  • Use external PLL = On
  • On
  • Off

If turned on, enables the rx_data_reset port.

Use common PLL(s) for receivers and transmitters Use external PLL = Off
  • On
  • Off
  • On—specifies that the compiler uses the same PLL for the LVDS receiver and transmitter.
  • Off—specifies that the compiler uses different PLLs for LVDS receivers and transmitters.

You can use common PLLs if you use the same input clock source, deserialization factor, pll_areset source, and data rates.

Enable self-reset on loss lock in PLL Use external PLL = Off
  • On
  • Off

If turned on, the PLL is reset when it loses lock.

Desired transmitter inclock phase shift
  • General, Functional mode = TX
  • Use external PLL = Off
Depends on Data rate.

Specifies the phase shift parameter used by the PLL for the transmitter.

Desired receiver inclock phase shift
  • General, Functional mode = RX
  • Use external PLL = Off
Depends on Data rate.

Specifies the phase shift parameter used by the PLL for the receiver.

Table 13.   Soft LVDS Parameters - Receiver Settings
Parameter Condition Allowed Values Description
Enable bitslip mode General, Functional mode = RX
  • On
  • Off

If turned on, enables the rx_data_align port.

Enable independent bitslip controls for each channel General, Functional mode = RX
  • On
  • Off

If turned on, enables the rx_channel_data_align port.

The rx_channel_data_align is an edge-sensitive bit slip control signal:

  • Each rising edge on this signal causes the data realignment circuitry to shift the word boundary by one bit.
  • The minimum pulse width requirement is one parallel clock cycle.
Enable rx_data_align_reset port
  • General, Functional mode = RX
  • Enable bitslip mode = On
  • Enable independent bitslip controls for each channel = Off
  • On
  • Off

If turned on, enables the rx_data_align_reset port.

Add extra register for rx_data_align port
  • General, Functional mode = RX
  • Enable bitslip mode = On
  • On
  • Off

If turned on, registers the rx_data_align port.

If you turn this option off, you must pre-register the rx_data_align[] port in the logic that feeds the receiver.

Bitslip rollover value
  • General, Functional mode = RX
  • Enable bitslip mode = On
1–11

Specifies the number of pulses before the circuitry restores the serial data latency to 0.

Use RAM buffer
  • On
  • Off

If turned on, the Soft LVDS IP core implements the output synchronization buffer in the embedded memory blocks.

This implementation option uses more logic than Use a multiplexer and synchronization register option but results in the correct word alignment.

Use a multiplexer and synchronization register
  • On
  • Off

If turned on, the Soft LVDS IP core implements a multiplexer instead of a buffer for output synchronization.

Use logic element based RAM
  • On
  • Off

If turned on, the Soft LVDS IP core implements the output synchronization buffer in the logic elements.

This implementation option uses more logic than Use a multiplexer and synchronization register option but results in the correct word alignment.

Register outputs General, Functional mode = RX
  • On
  • Off

If turned on, registers the rx_out[] port.

If you turn this option off, you must pre-register the rx_out[] port in the logic that feeds the receiver.

Table 14.   Soft LVDS Parameters - Transmitter Settings
Parameter Condition Allowed Values Description
Enable 'tx_outclock' output port
  • General, Functional mode = TX
  • PLL Settings, Use external PLL = Off
  • On
  • Off

If turned on, enables the tx_outclock port.

Every tx_outclock signal goes through the shift register logic, except in the following parameter configurations:

  • When the outclock_divide_by signal = 1
  • When the outclock_divide_by signal is equal to the deserialization_factor signal (for odd factors only), and the outclock_duty_cycle signal is 50
Tx_outclock division factor
  • General, Functional mode = TX
  • PLL Settings, Use external PLL = Off
  • Enable 'tx_outclock' output port = On
Depends on SERDES factor.

Specifies that the frequency of the tx_outclock signal is equal to the transmitter output data rate divided by the selected division factor.

Outclock duty cycle
  • General, Functional mode = TX
  • PLL Settings, Use external PLL = Off
  • Enable 'tx_outclock' output port = On
Depends on SERDES factor and Tx_outclock division factor.

Specifies the external clock timing constraints.

Desired transmitter outclock phase shift
  • General, Functional mode = TX
  • PLL Settings, Use external PLL = Off
  • Enable 'tx_outclock' output port = On
Depends on Data rate.

Specifies the phase shift of the output clock relative to the input clock.

Register 'tx_in' input port General, Functional mode = TX
  • On
  • Off

If turned on, registers the tx_in[] port.

If you turn this option off, you must pre-register the tx_in[] port in the logic that feeds the transmitter.

Clock resource
  • General, Functional mode = TX
  • Register 'tx_in' input port = On
  • tx_inclock
  • tx_coreclock

Specifies which clock resource registers the tx_in input port.

Enable 'tx_coreclock' output port General, Functional mode = TX
  • On
  • Off

If turned on, enables the tx_coreclock output port.

Clock source for 'tx_coreclock'
  • General, Functional mode = TX
  • Enable 'tx_coreclock' output port = On
  • Auto selection
  • Global clock
  • Regional clock
  • Dual-Regional clock

Specifies which clock resource drives the tx_coreclock output port.

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