Intel® MAX® 10 High-Speed LVDS I/O User Guide

ID 683760
Date 11/01/2021
Public
Document Table of Contents

2.3. Intel® MAX® 10 High-Speed LVDS Circuitry

The LVDS solution uses the I/O elements and registers in the Intel® MAX® 10 devices. The Soft LVDS IP core implements the serializer and deserializer as soft SERDES blocks in the core logic.

The Intel® MAX® 10 devices do not contain dedicated serialization or deserialization circuitry:

  • You can use I/O pins and core fabric to implement a high-speed differential interface in the device.
  • The Intel® MAX® 10 solution uses shift registers, internal PLLs, and I/O elements to perform the serial-to-parallel and parallel-to-serial conversions of incoming and outgoing data.
  • The Intel® Quartus® Prime software uses the parameter settings of the Soft LVDS IP core to automatically construct the differential SERDES in the core fabric.
Figure 2. Soft LVDS SERDESThis figure shows a transmitter and receiver block diagram for the soft LVDS SERDES circuitry with the interface signals of the transmitter and receiver data paths.


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