Intel® MAX® 10 High-Speed LVDS I/O User Guide

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ID 683760
Date 11/01/2021
Public
Document Table of Contents

2. Intel® MAX® 10 High-Speed LVDS Architecture and Features

The Intel® MAX® 10 devices use registers and logic in the core fabric to implement LVDS input and output interfaces.
  • For LVDS transmitters and receivers, Intel® MAX® 10 devices use the double data rate I/O (DDIO) registers that reside in the I/O elements (IOE). This architecture improves performance with regards to the receiver input skew margin (RSKM) or transmitter channel-to-channel skew (TCCS).
  • For the LVDS serializer/deserializer (SERDES), Intel® MAX® 10 devices use logic elements (LE) registers.

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