5.3. LVDS Transmitter and Receiver Debug and Troubleshooting
Although the focus of the board-level verification is to verify the FPGA functionality in your end system, you can take additional steps to examine the margins. Using oscilloscopes, you can examine the margins to verify the predicted size of the data-valid window, and the setup and hold margins at the I/O interface.
You can also use Signal Tap logic analyzer to perform system level verification to correlate the system against your design targets.