Intel® MAX® 10 High-Speed LVDS I/O User Guide

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ID 683760
Date 11/01/2021
Public
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3.4.1.2.2. Determining External PLL Clock Parameters for Soft LVDS Transmitter

To determine the ALTPLL IP core clock parameter for the Soft LVDS IP core transmitter, follow these steps in your design:
  1. Instantiate the Soft LVDS IP core transmitter using internal PLL.
  2. Compile the design up to Timing Analyzer timing analysis.
  3. In the Table of Contents section of the Compilation Report window, navigate to Timing Analyzer > Clocks.
  4. Note the clock parameters used by the internal PLL for the Soft LVDS IP core transmitter.
    In the list of clocks, clk0 is the fast clock.
Figure 14. Clock Parameters Example for Soft LVDS Transmitter


Configure the ALTPLL output clocks with the parameters you noted in this procedure and connect the clock outputs to the correct Soft LVDS clock input ports.

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