4.3.6. Guidelines: LVDS Receiver Logic Placement
To improve the performance of the Intel® Quartus® Prime Fitter, you can create Logic Lock regions in the device floorplan to confine the transmitter SERDES logic placement.
- The TCCS parameter is guaranteed per datasheet specification to the entire bank of differential I/Os that are located in the same side. This guarantee applies if the transmitter SERDES logic is placed within the LAB adjacent to the output pins.
- Constrain the transmitter SERDES logic to the LAB adjacent to the data output pins and clock output pins to improve the TCCS performance.
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