Intel® MAX® 10 High-Speed LVDS I/O User Guide

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ID 683760
Date 11/01/2021
Public
Document Table of Contents

4.1. High-Speed I/O Receiver Circuitry

The LVDS receiver circuitry uses the I/O elements and registers in the Intel® MAX® 10 devices. The deserializer is implemented in the core logic as a soft SERDES blocks.

In the receiver mode, the following blocks are available in the differential receiver datapath:

  • Deserializer
  • Data realignment block (bit slip)

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