Intel® MAX® 10 High-Speed LVDS I/O User Guide

ID 683760
Date 11/01/2021
Public
Document Table of Contents

3.4.3. Guidelines: LVDS Transmitter Channels Placement

To maintain an acceptable noise level on the VCCIO supply, observe the placement restrictions for single-ended I/O pins in relation to differential pads.

Intel recommends that you create an Intel® Quartus® Prime design, specify your device I/O assignments, and compile your design to validate your pin placement. The Intel® Quartus® Prime software verifies your pin connections against the I/O assignment and placement rules to ensure that the device operates properly.

You can use the Intel® Quartus® Prime Pin Planner Package view to ease differential I/O assignment planning:

  • On the View menu, click Show Differential Pin Pair Connections to highlight the differential pin pairing. The differential pin pairs are connected with red lines.
  • For differential pins, you only need to assign the signal to a positive pin. The Intel® Quartus® Prime software automatically assigns the negative pin if the positive pin is assigned with a differential I/O standard.

In Intel® MAX® 10 devices, the routing of each differential pin pair is matched. Consequently, the skew between the positive and the negative pins is minimal. The internal routes of both pins in a differential pair are matched even if the pins are non-adjacent.

The Soft LVDS IP core for Intel® MAX® 10 devices supports a maximum of 18 channels per IP instantiation. Each channel can support deserialization factor (parallel data width) from one to ten bits. When you are grouping channels for an application, you must consider the channel to channel skew during Fitter placement. To minimize skew, place all LVDS channels in the group side by side. For your PCB design, Intel recommends that you perform package skew compensation to minimize skew and maximize performance.
Note: For Intel® MAX® 10 devices, the Intel® Quartus® Prime software does not provide a package skew compensation report.

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