Intel® MAX® 10 High-Speed LVDS I/O User Guide

ID 683760
Date 11/01/2021

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Give Feedback Guidelines: LVDS RX Interface Using External PLL

You can instantiate the Soft LVDS IP core with the Use External PLL option. Using external PLL, you can control the PLL settings. For example, you can dynamically reconfigure the PLL to support different data rates and dynamic phase shifts. To use this option, you must instantiate the ALTPLL IP core to generate the various clock signals.

If you turn on the Use External PLL option for the Soft LVDS receiver, you require the following signals from the ALTPLL IP core:

  • Serial clock input to the rx_inclock port of the Soft LVDS receiver.
  • Parallel clock used to clock the receiver FPGA fabric logic.
  • The locked signal for Soft LVDS PLL reset port.