188.8.131.52. Guidelines: LVDS RX Interface Using External PLL
If you turn on the Use External PLL option for the Soft LVDS receiver, you require the following signals from the ALTPLL IP core:
- Serial clock input to the rx_inclock port of the Soft LVDS receiver.
- Parallel clock used to clock the receiver FPGA fabric logic.
- The locked signal for Soft LVDS PLL reset port.
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