Intel® MAX® 10 High-Speed LVDS I/O User Guide

ID 683760
Date 11/01/2021
Public
Document Table of Contents

4.3.1.2.1. ALTPLL Signal Interface with Soft LVDS Receiver

You can choose any of the PLL output clock ports to generate the LVDS interface clocks.

If you use the ALTPLL IP core as the external PLL source of the Soft LVDS receiver, use the source-synchronous compensation mode.

Table 8.  Example: Signal Interface Between ALTPLL and Soft LVDS Receiver with Even Deserialization Factor
From the ALTPLL IP Core To the Soft LVDS Receiver

Fast clock output (c0)

The serial clock output (c0) can only drive rx_inclock on the Soft LVDS receiver.

rx_inclock
Table 9.  Example: Signal Interface Between ALTPLL and Soft LVDS Receiver with Odd Deserialization Factor
From the ALTPLL IP Core To the Soft LVDS Receiver

Fast clock output (c0)

The serial clock output (c0) can only drive rx_inclock on the Soft LVDS receiver.

rx_inclock

Slow clock output (c1)

rx_syncclock

Read clock (c2) output from the PLL

rx_readclock

(clock input port for reading operation from RAM buffer and read counter)

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