Intel® MAX® 10 High-Speed LVDS I/O User Guide

ID 683760
Date 11/01/2021
Public
Document Table of Contents

6.4. Guidelines: Perform Board Level Simulations

After you determined the system requirements and finalized the board design constraints, use an electronic design automation (EDA) simulation tool to perform board-level simulations. Use the IBIS or HSPICE models of the FPGA and the target LVDS device for the simulation.

The board-level simulation ensures optimum board setup where you can determine if the data window conforms to the input specification (electrical and timing) of the LVDS receiver.

You can use the programmable pre-emphasis feature on the true LVDS output buffers, for example, to compensate for the frequency-dependent attenuation of the transmission line. With this feature, you can maximize the data eye opening at the far end receiver especially on long transmission lines.

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