Intel® MAX® 10 High-Speed LVDS I/O User Guide

ID 683760
Date 11/01/2021
Public
Document Table of Contents

7.2. Soft LVDS Interface Signals

Depending on parameter settings you specify, different signals are available for the Soft LVDS IP core.
Table 15.  Transmitter Interface Signals
Signal Name Direction Width (Bit) Description
pll_areset Input 1

Asynchronously resets all counters to the initial values.

tx_data_reset Input <n>

Asynchronous reset for the shift registers, capture registers, and synchronization registers for all channels.

  • This signal is used if Use external PLL parameter setting is turned on.
  • This signal does not affect the data realignment block or the PLL.
tx_in[] Input <m>

This signal is parallel data that Soft LVDS IP core transmits serially.

Input data is synchronous to the tx_coreclock signal. The data bus width per channel is the same as the serialization factor (SF).

tx_inclock Input 1

Reference clock input for the transmitter PLL.

The parameter editor automatically selects the appropriate PLL multiplication factor based on the data and reference clock frequency.

tx_coreclock Output 1

Output clock that feeds non-peripheral logic.

FPGA fabric–transmitter interface clock—the parallel transmitter data generated in the FPGA fabric is clocked with this clock.

tx_locked Output 1

Provides the LVDS PLL status:

  • Remains high when the PLL is locked to the input reference clock.
  • Remains low when the PLL fails to lock.
tx_out[] Output <n>

Serialized LVDS data output signal of <n> channels.

tx_out[(<n>-1)..0] drives parallel data from tx_in[(<J> × <n>)-1 ..0] where <J> is the serialization factor and <n> is the number of channels. tx_out[0] drives data from tx_in[(<J>-1)..0]. tx_out[1] drives data from the next <J> number of bits on tx_in.

tx_outclock Output 1

External reference clock.

The frequency of this clock is programmable to be the same as the data rate.

Table 16.   Receiver Interface Signals

signal Name

Direction

Width (Bit)

Description

rx_data_reset Input <n>

Asynchronous reset for all channels, excluding the PLL.

  • This signal is available if Use external PLL parameter setting is turned on.
  • You must externally synchronize this signal with the fast clock.
rx_in[] Input <n>

LVDS serial data input signal of <n> channels.

rx_in[(<n>-1)..0] is deserialized and driven on rx_out[(<J> × <n>)-1 ..0] where <J> is the deserialization factor and <n> is the number of channels. rx_in[0] drives data to rx_out[(<J>-1)..0]. rx_in[1] drives data to the next <J> number of bits on rx_out.

rx_inclock Input 1

LVDS reference input clock.

The parameter editor automatically selects the appropriate PLL multiplication factor based on the data rate and reference clock frequency selection.

rx_coreclk Input <n>

LVDS reference input clock.

  • Replaces the non-peripheral clock from the PLL.
  • One clock for each channel.
rx_locked Output 1

Provides the LVDS PLL status:

  • Stays high when the PLL is locked to the input reference clock.
  • Stays low when the PLL fails to lock.
rx_out Output <m>

Receiver parallel data output.

The data bus width per channel is the same as the deserialization factor (DF).

rx_outclock Output 1

Parallel output clock from the receiver PLL.

  • This signal is not available if you turn on the Use external PLL parameter setting.
  • The FPGA fabric–receiver interface clock must be driven by the PLL instantiated through the ALTPLL parameter editor.
rx_data_align Input 1

Controls the byte alignment circuitry.

You can register this signal using the rx_outclock signal.

rx_data_align_reset Input 1

Resets the byte alignment circuitry.

Use the rx_data_align_reset input signal if:

  • You need to reset the PLL during device operation.
  • You need to re-establish the word alignment.
rx_channel_data_align Input <n>

Controls byte alignment circuitry.

rx_cda_reset Input <n>

Asynchronous reset to the data realignment circuitry. This signal resets the data realignment block.

The minimum pulse width requirement for this reset is one parallel clock cycle.

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