4.1.2. Data Realignment Block (Bit Slip)
To align the data manually, use the data realignment circuit to insert a latency of one RxFCLK cycle . The data realignment circuit slips the data one bit for every RX_DATA_ALIGN pulse. You must wait at least two core clock cycles before checking to see if the data is aligned. This wait is necessary because it takes at least two core clock cycles to purge the corrupted data.
An optional RX_CHANNEL_DATA_ALIGN port controls the bit insertion of each receiver independently of the internal logic. The data slips one bit on the rising edge of RX_CHANNEL_DATA_ALIGN.
The RX_CHANNEL_DATA_ALIGN signal has these requirements:
- The minimum pulse width is one period of the parallel clock in the logic array.
- The minimum low time between pulses is one period of the parallel clock.
- The signal is edge-triggered.
- The valid data is available two parallel clock cycles after the rising edge of RX_CHANNEL_DATA_ALIGN.