Intel® MAX® 10 High-Speed LVDS I/O User Guide

ID 683760
Date 11/01/2021
Public
Document Table of Contents

3.4.1.1.2. Instantiate Soft LVDS IP Core with External PLL4.3.1.1.2. Instantiate Soft LVDS IP Core with External PLL

You can set the Soft LVDS IP core to build only the SERDES components but use an external PLL source.
  • To use this method, turn on the Use external PLL option in the PLL Settings tab.
  • Follow the required clock setting to the input ports as listed in the notification panel.
  • You can create your own clocking source using the ALTPLL IP core.
  • Use this method to optimize PLL usage with other functions in the core.

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