6.3. Guidelines: Determine Board Design Constraints
The time margin for the LVDS receiver (indicated by the RSKM value) is the timing budget allocation for board level effects such as:
- Skew—these factors cause board-level skew:
- Board trace lengths
- Connectors usage
- Parasitic circuits variations
- Jitter—jitter effects are derived from factors such as crosstalk.
- Noise—on board resources with imperfect power supplies and reference planes may also cause noise.
To ensure successful operation of the Soft LVDS IP core receiver, do not exceed the timing budget.
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