Intel® MAX® 10 High-Speed LVDS I/O User Guide

Download
ID 683760
Date 11/01/2021
Public
Document Table of Contents

3.4.1.2.1. ALTPLL Signal Interface with Soft LVDS Transmitter

You can choose any of the PLL output clock ports to generate the LVDS interface clocks.

If you use the ALTPLL IP core as the external PLL source of the Soft LVDS transmitter, use the source-synchronous compensation mode.

Table 6.  Example: Signal Interface between ALTPLL and Soft LVDS Transmitter
From the ALTPLL IP Core To the Soft LVDS Transmitter

Fast clock output (c0)

The fast clock output (c0) can only drive tx_inclock on the Soft LVDS transmitter.

tx_inclock

Slow clock output (c1)

tx_syncclock

Did you find the information on this page useful?

Characters remaining:

Feedback Message