AN 307: Intel® FPGA Design Flow for AMD* Xilinx* Users

ID 683562
Date 9/08/2023

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4.2.3. Converting Multipliers

The following section discusses converting instances of the AMD* Xilinx* Multiplier Core to Intel® FPGA Multiplier IP cores.

Intel® provides two IP cores for implementing multiply, multiply- accumulate, and multiply-add functions using DSP blocks or logic resources:

  • The LPM_MULT IP core, which performs multiply functions only.
  • The Intel® FPGA Multiply Adder IP core, which performs multiply, multiply-add, or multiply-accumulate functions.
To perform the conversion:
  1. In the original code, identify whether the dataa and datab ports have the same sign.
  2. If the ports have the same sign, replace the AMD* Xilinx* Multiplier Core with the LPM_MULT IP core,
  3. Otherwise, replace with the Intel® FPGA Multiply Adder IP core.
  4. In the IP Catalog, click the selected IP core.
  5. Assign the parameters and generate HDL Intel® FPGA IP core.
For more information, refer to Inferring Multipliers in the Recommended HDL Coding Styles chapter of Intel® Quartus® Prime Pro Edition User Guide: Design Recommendations.