AN 307: Intel® FPGA Design Flow for AMD* Xilinx* Users

ID 683562
Date 9/08/2023

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Document Table of Contents Create Timing Constraints with the Timing Analyzer Text Editor

The Intel® Quartus® Prime Timing Analyzer (Tools > Timing Analyzer ) reads and writes timing constrains in the industry-standard Synopsys* Design Constraint (SDC) format. The Timing Analyzer provides a GUI interface that allows you to manually create and modify timing constraints.
Note: Ensure that the project is open before using the Timing Analyzer.
  • To create a new SDC file from the Timing Analyzer, click File > New SDC File.
  • To apply templates for SDC constraints, click Edit > Insert Template command.

    The Timing Analyzer Text Editor uses syntax coloring for SDC reserved words and comments.

    Figure 6.  Timing Analyzer Text Editor