AN 307: Intel® FPGA Design Flow for AMD* Xilinx* Users

ID 683562
Date 9/08/2023

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Document Table of Contents Error Correction Code (ECC)

AMD* Xilinx* and Intel® FPGA RAMs use Error Correction Code (ECC) to detect errors in the memory array, and present the corrected single-bit error data on the output.

Table 45.  Comparison of ECC Support and Status Output Signals for Intel® FPGA and AMD* Xilinx* RAMs
  Intel® FPGA AMD* Xilinx*
ECC support
  • Built-in support for eSRAM and M20K type of Embedded Memory Block selected in simple dual-port mode.
  • Intel® FPGA also provides a dedicated soft IP ECC core that is flexibly implemented in your design, and is not restricted by the type of memory block used. For more information about the ECC IP core, refer to the Intel® FPGA Integer Arithmetic IP Cores User Guide.
For UltraScale+* and 7-series devices in simple dual-port RAM.
Status Signal Indicates the status of the M20K block using a three-bit status flag eccstatus[1..0] Indicates the status of the data read using two status outputs:
Note: Intel® FPGA does not support using ECC with the byte-enable or coherent read features.

ECC Parity Flip

The ECC parity flip feature is available only on Intel Agilex® 7 and Intel® Stratix® 10 devices.

The ECC parity flip feature dynamically flips the parity value generated in the encoder of M20K blocks to observe the ECC behavior through simulation.

When the ECC Encoder Bypass (eccencbypass) port is high, the built-in ECC encoder values are XOR-ed with the 8 parity bits through the parity ports to generate a new set of encoder value. When the ECC Encoder Bypass port is low, the encoder generates the parity bits according to the data input during a write process.

The following table shows an example to construct an 8-bit data width for the parity port.

Table 46.  Example of Setting the 8-Bit Parity Ports
Parity Bit Sequence ECC Feature Is the ECC Decoder able to Recognize and Correct the Data Bit?
00000001 Single-error correction Yes
00000011 Double-adjacent-error correction Yes
00000111 Triple-adjacent-error correction Yes
00000101 Triple-adjacent-error correction Yes
00010011 Non-adjacent double/triple correction/detection No guarantee

For more information about ECC, refer to the chapter about Embedded Memory Blocks in your target device handbook.