AN 307: Intel® FPGA Design Flow for AMD* Xilinx* Users

ID 683562
Date 9/08/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.3.6. Design Implementation

The implementation flow in the Vivado* software places and routes the netlist onto the FPGA device resources based on the constraints of the design. The Finalize flow in the Intel® Quartus® Prime Pro Edition software consists of the Plan, Place, Route, Retime 11, and Finalize compilation stages. Start the Finalize flow by clicking Fitter in the Compilation Dashboard.

Table 17.  Design Implementation Comparison
GUI Feature AMD* Xilinx* Vivado* Software Intel® Quartus® Prime Pro Edition Software
Design Implementation Implementation Fitter (Plan, Place, Route, Retime11 and Finalize)


The Intel® Quartus® Prime Pro Edition Compiler offers unique features, such as:

  • Snapshot Viewer—analyze the results of a compilation snapshot to evaluate the design before running the next stage, or running a full compilation. Compiler snapshots can be used to isolate potential problems.
  • Incremental Fitter Optimizations—run and optimize Fitter stages incrementally. Each Fitter stage generates detailed reports. You can view detailed report data and analyze the timing of each stage while downstream stages are still running.
  • Hyper-Aware Design Flow—use Hyper-Retiming and Fast Forward compilation for the highest performance in Intel Agilex® 7 and Intel® Stratix® 10 devices.

You can start each phase in the compilation flow independently either from GUI or from the command line. The Compilation Dashboard allows you to use the tools and features of the software and monitor progress from a flow-based layout.


The Assignments > Settings > Compiler Settings > Advanced Settings (Fitter) dialog box allows you customize the place and route of the compilation flow.

11 Retime and Fast-Forward Compilation available only for Intel Agilex® 7 and Intel® Stratix® 10 devices.