AN 307: Intel® FPGA Design Flow for AMD* Xilinx* Users

ID 683562
Date 9/08/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents Snapshot Viewer

Use the Snapshot Viewer to evaluate your design by analyzing the results of compilation snapshots before you run the next compilation stage or before you run a full compilation.

From the Flow Navigator in Snapshot Viewer, you can run timing closure and design after the Fitter Plan, Place, Route, or Finalize stages.